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Voyager
Voyager
4,312 Views
Registered: ‎05-21-2015

Slow DDR3 SDRAM on an Arty

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Hello!

 

I'm trying to get a DDR3/SDRAM controller for my Arty board.  The board contains a MT41K128M16XX-125 part that would nominally run at an 800MHz command clock although, I've been advised that the Artix-7/35T/-1L part on the Arty can only handle the -125 part in it's -15E mode (DDR1333, 9-9-9 at 667MHz).  The chip is wired for 1.35V operation. 

 

What I would like to do is to synchronize the memory controller's logic with the logic I have on the board.  I'm running my logic on a 200MHz clock, so I'd like to run the memory from a 200MHz clock as well.  According to the DDR3 specification, it should be possible to run this chip from a 400MHz command clock, issuing 2 commands per clock (4 data words per clock).

 

However, when I run the MIG setup, it refuses to let me input a 2500ps clock with a 2:1 PHY to controller clock ratio.  Instead, it insists that "The Memory Part MT41K128M16xx-15E with the Voltage 1.35V supports the clock period range 3000-3300.  Either change the clock period or select a different Memory Part Voltage."

 

Can you recommend any way of doing this where I can keep both the MIG generated controller, as well as my own logic, using the same 200MHz clock?  The DDR3 specification indicates this is entirely within bounds ...

 

Thanks!

 

Dan

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Visitor scott.powell
Visitor
7,782 Views
Registered: ‎08-31-2016

Re: Slow DDR3 SDRAM on an Arty

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Hello Dan,

 

This is a limitation not of the DDR3L component, but of the -1L speed-grade Artix-7. Per the DS181 "Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics" the maximum transfer rate for DDR3L in a -1L speed-grade for a 2:1 Memory Controller is 620 Mbps, and for a 4:1 Memory Controller it is 667 Mbps. For a controller clock rate of 200Mhz in a 2:1 controller, this infers an 800 Mbps transfer rate.

 

With that said, only the -3 speed-grade Artix-7 supports 800 Mbps transfer rate in a 2:1 memory controller, regardless of 1.35V or 1.5V operation. 

 

Sorry this does not solve your problem, but hopefully sheds some light on the cause.

 

- Scott

 

 

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Visitor scott.powell
Visitor
7,783 Views
Registered: ‎08-31-2016

Re: Slow DDR3 SDRAM on an Arty

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Hello Dan,

 

This is a limitation not of the DDR3L component, but of the -1L speed-grade Artix-7. Per the DS181 "Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics" the maximum transfer rate for DDR3L in a -1L speed-grade for a 2:1 Memory Controller is 620 Mbps, and for a 4:1 Memory Controller it is 667 Mbps. For a controller clock rate of 200Mhz in a 2:1 controller, this infers an 800 Mbps transfer rate.

 

With that said, only the -3 speed-grade Artix-7 supports 800 Mbps transfer rate in a 2:1 memory controller, regardless of 1.35V or 1.5V operation. 

 

Sorry this does not solve your problem, but hopefully sheds some light on the cause.

 

- Scott

 

 

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Voyager
Voyager
4,279 Views
Registered: ‎05-21-2015

Re: Slow DDR3 SDRAM on an Arty

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Okay, that explains why the controller can't have a memory clock period less than 3ns, and the DDR3 spec sheet explains why it cannot be greater than 3.3ns.  Further, the chart you pointed me at, together with your data rate explanation, explains why the memory controller can't do 2:1 memory access with a clock period less than 3.225. 

 

I guess that leaves me with some choices, if I want the clock rates to work out "nicely":

1. Picking a system clock in the range of 76 to 83 MHz (for the 4:1 clock),

2. Picking a system clock in the range of 152 to 155 MHz (for the 2:1 clock)

3. Just accept a clock transfer.

 

Hmm ... I wonder if I might run my system clock at 160MHz, and the memory clock at 80MHz using a 4:1 interface, and do a nice synchronous transfer between the two every other clock?

 

At any rate, thanks for your explanation.  Sadly, it means I have a lot to rethink, but I do appreciate the help.

 

Dan

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Visitor scott.powell
Visitor
4,275 Views
Registered: ‎08-31-2016

Re: Slow DDR3 SDRAM on an Arty

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It sounds like you're on the right track now. The 4:1 controller can be nice if you are in a slower speed-grade part and you are worried about meeting timing, but of course that is speculative and non-quantitative on my part.

 

Just to be clear, you'll need to choose a "Clock Period" (as referenced in the Controller Options of the MIG GUI) that allows you to choose a "Input Clock Period" (after clicking 'Next' > Memory options) that you have access to or can generate locally. That clock, called sys_clk_i, is the input to the MMCM internal to the DDR controller that creates the rest of the required clocks, including the "ui_clk", which is the user side (4:1 or 2:1 divided down of your DDR clock speed) of the controller. It is this clock that you desired to equal the frequency of the clock that you referred to as "my system clock" I'm guessing, and is different from sys_clk_i. 

 

Sorry, that is a mouthful, but I wanted to make sure we were using the same semantics.

 

Now, if you want utilize a known integer relationship between a 160Mhz "my system clock" and an 80Mhz ui_clk to avoid a subset of asynchronous transactions, that may or may not be worthwhile! ... perhaps a good discussion for a timing closure thread under a different forum topic. 

 

Good luck!

 

- Scott

 

 

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