01-22-2019 09:30 PM
We are facing an issue with respect to Simulating the MIG design for a Spartan 6 FPGA.
We are able to write data into the write FIFO of the MCB and the c3_p0_write_count is increasing.
But when we are sending the command to Command FIFO the c3_p0_cmd_empty signal goes low, but writing to memory is not happening.
Attaching the Simulation screenshot.
01-29-2019 01:56 AM
Is this simulation coming from teh example design?
Have you tried on Hardware? Does teh interface work there. Wondering if this is a simulation issue instead of a functional one.
01-29-2019 08:26 PM
It is working in the Hardware.
But we need the simulation to be done for the verification environment.
01-30-2019 02:03 AM
I understand that but we need to establish if this is a simulation or functional issue, if you have HW i would recommend trying the design on it so we can understand where the failure lies.