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Explorer
Explorer
3,521 Views
Registered: ‎01-18-2011

System Clock, PLL Location, and Constraints

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Hello!

 

UG586, pp 136:

 

"The PLL is required to be in the bank that supplies the clock to the memory to meet the specified interface performance. The system clock input is also strongly recommended to be in this bank. The MIG tool follows these two rules whenever possible. The exception is a 16-bit interface in a single bank where there might not be pins available for the clock input. In this case, the clock input needs to come from an adjacent (???) bank through the frequency backbone to the PLL. The system clock input to the PLL must come from clock capable I/O."

 

Why should clock input to be driven from adjacent bank only ? What does it give in comparison with input clock driving from not adjacent bank, but in the same column ?

 

Regards,

Sergey

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Explorer
Explorer
2,462 Views
Registered: ‎01-18-2011

Re: System Clock, PLL Location, and Constraints

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I would say that sysclock  must come from CCIO only, whether it is same bank or another bank in the same column.

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Xilinx Employee
Xilinx Employee
3,504 Views
Registered: ‎07-11-2011

Re: System Clock, PLL Location, and Constraints

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Hi

 

I expect this is to meet timing,  adjacent banks  minimize skew added across banks.

If your requirement is X16 please refer below link for more details

 

http://www.xilinx.com/support/answers/41752.htm

 

Regards,

 

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Explorer
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Registered: ‎01-18-2011

Re: System Clock, PLL Location, and Constraints

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Thank you!

 

http://www.xilinx.com/support/answers/40603.htm

 

"The clock input (sys_clk) can now be input on any CCIO in the column where the memory interface is located; this includes CCIO in banks that do not contain the memory interface, but must be in the same column as the memory interface. The PLL must be located in the bank containing the clock sent to the memory. To route the input clock to the memory interface PLL, the CMT backbone must be used. With the MIG implementation, one spare interconnect on the backbone is available that can be used for this purpose."

 

i.e. CCIO must be in the same column. There is not requirement that CCIO must be in the adjacent bank. Is it correct?

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

Re: System Clock, PLL Location, and Constraints

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Hi,

 

As far as MIG is concerned  sysclock  must come from CCIO only , whether it is same bank or adjacent.bank in the same column.

 

Regards,

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Explorer
Explorer
2,463 Views
Registered: ‎01-18-2011

Re: System Clock, PLL Location, and Constraints

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I would say that sysclock  must come from CCIO only, whether it is same bank or another bank in the same column.

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