02-16-2017 07:46 AM
I'm using two Two DDR which is resides in non column but horizontally adjacent for FPGA ( C0 : -bank no 33 and 34 , C1:- bank no 12 and 13)
Now i'm using two master to drive controller respectively , but my user logic has to work in one clk to sync with all other protocal ,
guys please tell me how to share a one system clock for both MIG to get same c0_ui_clk and c1_ui_clk , so that I can use either of clk to sync all my logic.
please tell me how to share a system clock when its in not same column,
"I have one idea that declaring both MIG in No buffer for system clock , later I can use one MRCC connected clock to drive
PLL->bufg then i can use it for system clock for both MIG " this Technic will it works???
please reply , its urgent I have very less time
02-16-2017 09:25 AM
The system clock should be driven from the same I/O column even if you use NO Buffer option.
Check the clocking guidelines from below AR.
02-16-2017 09:24 PM
Thanks for replay sathish,
sathish in my case both ddr are not in same column , but i has to drive it to sync the clock can i use any one locally driven same clock to as system clock for both ddr in this case both will work ??
1)Actual my problem is I'm driving two DDR throughTwo AXI master (user logic which is working in VC709 board) and with axi interconnet ip ,I'm using repective C0/C1_ui_clk to in my master code and axi interconnect respectively , here C0 ddr are responding and can read/write but C1 ddr is not worikng/responding how to make it work ,
IMP:-I have not ticked DCI option in GUI of MIG (where Im using DDR at 800 mhz),
whats the important of DCI opition , should it be ticked when we are using two/more controller
i'm looking for your reply