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Participant kmwilliams
Participant
120 Views
Registered: ‎05-11-2018

Two 32-bit MIGs to implement one LPDDR2 64-bit interface on Artix-7

I need to implement a 64-bit LPDDR2 600 MHz DDR (300 MHZ clock) memory interface on an Artix-7 200 FPGA.  The Memory Interface Generator will only support up to a 32 bit interface when using LPDDR2.  This means I will have to use two separate MIGs implemented the same but with different pin/bank targets. I know it is recommended that the reference clock (in my implementation reference/sys_clk are the same) should be on a clock pin in the Address/Ctrl bank.  Well there are two MIGs in this implementation.  If I have separate clock pin p/n pairs for the two MIGs, there won't be any guarantee that the two MIGs would operate synchronously.  The two MIGs will generate also generate two separate user clocks. How do I generate/use the variousl clocks and insure the two MIGs will operate synchronously?  Is this possible? 

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3 Replies
Moderator
Moderator
67 Views
Registered: ‎11-28-2016

Re: Two 32-bit MIGs to implement one LPDDR2 64-bit interface on Artix-7

Hello @kmwilliams,

In these situations if you can fit both 32-bit interfaces in he same I/O column in the FPGA then you can share a common system clock as described in in the "Sharing sys_clk between Controllers" section starting on page 212 og UG586. A link is in my signature. Overall there is no way to guarantee that both controllers will work synchronously.  I've seen customers design their own logic that would present a single app_interface at the top level which then drives the app_interfaces for the two controllers beneath it plus keeps them synchronized at the top level.

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Participant kmwilliams
Participant
59 Views
Registered: ‎05-11-2018

Re: Two 32-bit MIGs to implement one LPDDR2 64-bit interface on Artix-7

ryana,

Is there a limitation in the FPGA or MIG that would prevent expanding a 32-bit LPDDR2 MIG to a 64-bit MIG such that a single usr_clk is generated similar to what can be done with a DDR3?  Is the reason an 64-bit LPDDR2 is not supported in the MIG tool because of a technical limitation or just merely the fact that this was never implemented in the the MIG tool?

Kerry

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Moderator
Moderator
51 Views
Registered: ‎11-28-2016

Re: Two 32-bit MIGs to implement one LPDDR2 64-bit interface on Artix-7

Hello @kmwilliams,
The LPDDR2 IP was only created to support up to a 32-bit interface since the target applications were single component point-to-point interfaces and x16 or x32 were the common component widths at the time. 

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