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Adventurer
Adventurer
154 Views
Registered: ‎04-06-2017

USE DDR3 as the program memory for CPU core

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I create a module similar to CPU core. It uses DDR3 as the program memory. Will it a be a problem that MIG does not do read  code stored in DDR3 in a constant speed because the waiting time of of app_rdy is not a constant and can not be predicted. Will the cpu have to wait for a new code to be read out? In that case, one can not tell how many clocks will be spent for one code.

Thank you.

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Voyager
Voyager
103 Views
Registered: ‎02-01-2013

Re: USE DDR3 as the program memory for CPU core

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OTS = Off The Shelf--i.e., you bought it instead of making it yourself

Strict HW processing is a straight-line HW processing pipe.  It's the best way to guarantee an answer in a certain number of clock ticks. e.g., input <clock> process 0 <clock> process 1 <clock> process 2....  <clock> process n <clock> answer. DDR memory would not be used to store the processing steps, as they'd all be hardcoded as HW functions inside the FPGA.

A cache miss is a common occurrence for a microprocessor or a CPU. It results in a longer processing time when the CPU has to wait for the cache to fetch new instructions from main memory. Proper coding can reduce the likelihood of a cache miss, but it can't completely eliminate the possibility, especially if the CPU is multi-tasking. That's why I mentioned the alternatives--in case that's a critical point for you.

-Joe G.

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Voyager
Voyager
142 Views
Registered: ‎02-01-2013

Re: USE DDR3 as the program memory for CPU core

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Apparently, it might be a problem for you, since you're bringing up the issue of non-deterministic read times. 

Two words: instruction cache.

Even then, if precise response time is critical, you'll need to create well-written CPU code that will allow your cache to stay ahead.

-Joe G.

 

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Adventurer
Adventurer
132 Views
Registered: ‎04-06-2017

Re: USE DDR3 as the program memory for CPU core

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I plan to use block RAM in FPGA as cathe. Does "allow your cache to stay ahead" mean not to jump backwords? Actually if it jumps forword and out of the cathe. The new instruction may not be read in time. I am wondering will this occurs for computer? The time cost for the same instruction does not always the same?
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Voyager
Voyager
126 Views
Registered: ‎02-01-2013

Re: USE DDR3 as the program memory for CPU core

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A typical cache system should be able to keep ahead of a simple branch, forward or backward. It's the conditional, multi-way branching that can lead to problems.

If you need single-clock precision of your processing timing, the most straightforward way to get that is by using strict HW processing. Next best would be using a custom micro-controller.* Then using an OTS micro-controller. Then using a CPU.

-Joe G.

* My boss still kids me about J++, a SW 'language' I wrote years ago to support a custom micro-controller that I built for a Spartan-3 design. The 'compiler' for J++ was an Excel spreadsheet. :-)

 

Adventurer
Adventurer
117 Views
Registered: ‎04-06-2017

Re: USE DDR3 as the program memory for CPU core

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Sorry for my ignorance, what is "OTS"?
"the most straightforward way to get that is by using strict HW processing", Do you mean that not to use any instruction, use the only the resources of FPGA to create the hardware system. Since no instruction is needed, the DDR3 is not used for this purpose?
Do you know if a computer will have this problem: a jump operation out of the cathe, insruction in DDR3 is not read in a constant delay?
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Voyager
Voyager
110 Views
Registered: ‎08-16-2018

Re: USE DDR3 as the program memory for CPU core

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you need to cache that code memory. DDR memories are at their happiest when reading/ writing data chunks.

Voyager
Voyager
104 Views
Registered: ‎02-01-2013

Re: USE DDR3 as the program memory for CPU core

Jump to solution

 

OTS = Off The Shelf--i.e., you bought it instead of making it yourself

Strict HW processing is a straight-line HW processing pipe.  It's the best way to guarantee an answer in a certain number of clock ticks. e.g., input <clock> process 0 <clock> process 1 <clock> process 2....  <clock> process n <clock> answer. DDR memory would not be used to store the processing steps, as they'd all be hardcoded as HW functions inside the FPGA.

A cache miss is a common occurrence for a microprocessor or a CPU. It results in a longer processing time when the CPU has to wait for the cache to fetch new instructions from main memory. Proper coding can reduce the likelihood of a cache miss, but it can't completely eliminate the possibility, especially if the CPU is multi-tasking. That's why I mentioned the alternatives--in case that's a critical point for you.

-Joe G.