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969 Views
Registered: ‎05-09-2018

Ultrascale DDR4 DQS PCB Design Guidelines

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The UG583 Ultrascale design guidelines specify 66 Ohms for DQS differential impedance with DIMMs (p. 81). Other sections specify a DQS differential impedance of 76 to 90 Ohms (p. 68) with DRAM soldered down. Why is the DQS differential impedance lower for DIMMs? Other SoC memory controllers typically specify a higher impedance for L1 and L2 (~85 Ohms).

 

Thanks.

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Xilinx Employee
Xilinx Employee
1,155 Views
Registered: ‎03-14-2016

Re: Ultrascale DDR4 DQS PCB Design Guidelines

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Hello,

We recommend 66 ohm DQS with a DIMM because of the series resistors on the DIMM.

We have run simulations to confirm this.

Thank you,
Sam

 

3 Replies
Xilinx Employee
Xilinx Employee
925 Views
Registered: ‎03-14-2016

Re: Ultrascale DDR4 DQS PCB Design Guidelines

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Hello, 

In both cases the breakout is 86 ohms.  I am working on getting an answer as to why we recommend 66 ohms for DIMM and 76 ohms for components.

Thank you,
Sam

 

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Xilinx Employee
Xilinx Employee
1,156 Views
Registered: ‎03-14-2016

Re: Ultrascale DDR4 DQS PCB Design Guidelines

Jump to solution

Hello,

We recommend 66 ohm DQS with a DIMM because of the series resistors on the DIMM.

We have run simulations to confirm this.

Thank you,
Sam

 

904 Views
Registered: ‎05-09-2018

Re: Ultrascale DDR4 DQS PCB Design Guidelines

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Thanks for the prompt reply!

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