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1,640 Views
Registered: ‎09-14-2017

Ultrascale+ DDR4 example design(ies) simulation issue

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Hello,

 

When I exported simulation(ies) from DDR4 exam project(vivado reference design/vivado 18.1),

below warnings are comming!!! (so many things...)

--------------------------------------------------------------------------------------------------------------------------

Model:WARNING: Reading unwritten address: C:0 BG:1 B:3 R:bd C:7c dm:0 @22051.5 ns

.

.

.

Model:WARNING: Reading unwritten address: C:0 BG:1 B:3 R:bd C:7b dm:0 @22054.5 ns

Model:WARNING: Reading unwritten address: C:0 BG:1 B:3 R:bd C:7b dm:1 @22054.5 ns

--------------------------------------------------------------------------------------------------------------------------

I already checked AR# 65732 and "https://forums.aws.amazon.com/thread.jspa?messageID=795133"

However these were not helpful current issue. There was no effect... :(

Actually, the simulation result was fine, but so many warnings were bother me.

 

Could you please let me know how to turn off these warning messages?

I just used your reference DDR4 exam design..

Please find the attachment which is simulation results.

 

I look forward to your quick replying.

Thanks, BR

 

Victorr

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Moderator
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1,960 Views
Registered: ‎02-11-2014

Re: Ultrascale+ DDR4 example design(ies) simulation issue

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Hello yd.je@samsung.com,

 

I did get a reply from Micron and I have figured out how to silence the warning messages. I will end up making an Answer Record with the data in it for future reference.

 

Basically depending on your core configuration before you build the example design, the test bench will instantiate a memory model for each component. So in my example I have been working with 4 x16 components (DW = 64) so the memory model is instantiated 4 times for each component

 

micron_ddr4_model.PNG

 

So in my sim_tb_top.sv I added the following RTL right after the wire/register declarations to turn off the warning messages:

 

 //===========================================================================
     //                         Disable Warning Messages
     //===========================================================================
    
    initial begin
    #1ps;         //(any time here should work, as long as it is before the writes)
    sim_tb_top.mem_model_x16.mem.memModels_Ri2[0].memModel2[0].ddr4_model.set_memory_warnings(0,0);
    sim_tb_top.mem_model_x16.mem.memModels_Ri2[0].memModel2[1].ddr4_model.set_memory_warnings(0,0);
    sim_tb_top.mem_model_x16.mem.memModels_Ri2[0].memModel2[2].ddr4_model.set_memory_warnings(0,0);
    sim_tb_top.mem_model_x16.mem.memModels_Ri2[0].memModel2[3].ddr4_model.set_memory_warnings(0,0);
    end

 

Please use this logic to apply it to your application and let me know if you have any issues. To turn the warning messages back on you need to set_memory_warnings(1,1) using the same logic above in your test bench.

 

Thanks,

Cory

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8 Replies
Moderator
Moderator
1,594 Views
Registered: ‎02-11-2014

Re: Ultrascale+ DDR4 example design(ies) simulation issue

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Hello yd.je@samsung.com,

 

Your simulation results did not attach to your original post. Please include your XCI file as well.

 

Thanks,
Cory

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1,569 Views
Registered: ‎09-14-2017

Re: Ultrascale+ DDR4 example design(ies) simulation issue

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Hi,

Thank you for replying.

Please check attachments.(.xci & log)

Thanks,

BR,

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1,545 Views
Registered: ‎09-14-2017

Re: Ultrascale+ DDR4 example design(ies) simulation issue

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How is this problem going?
I am wating for your reply~

Thanks,
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Moderator
Moderator
1,538 Views
Registered: ‎02-11-2014

Re: Ultrascale+ DDR4 example design(ies) simulation issue

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Hello yd.je@samsung.com,

 

I am am currently in contact with Micron to get a better understanding of how their warning message functions into the model work. They are not documented well in their current state.

 

Thanks,

Cory

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1,534 Views
Registered: ‎09-14-2017

Re: Ultrascale+ DDR4 example design(ies) simulation issue

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Hello, coryb

 

Thanks for your answer.

If you have any update, please notice to me.

 

Thanks,

yd.je

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1,489 Views
Registered: ‎09-14-2017

Re: Ultrascale+ DDR4 example design(ies) simulation issue

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How is this problem going?

Is there no reply from micron?

If so, did you have no any idea to solve this issue?
I am very wating for your reply~


Thanks,

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Moderator
Moderator
1,961 Views
Registered: ‎02-11-2014

Re: Ultrascale+ DDR4 example design(ies) simulation issue

Jump to solution

Hello yd.je@samsung.com,

 

I did get a reply from Micron and I have figured out how to silence the warning messages. I will end up making an Answer Record with the data in it for future reference.

 

Basically depending on your core configuration before you build the example design, the test bench will instantiate a memory model for each component. So in my example I have been working with 4 x16 components (DW = 64) so the memory model is instantiated 4 times for each component

 

micron_ddr4_model.PNG

 

So in my sim_tb_top.sv I added the following RTL right after the wire/register declarations to turn off the warning messages:

 

 //===========================================================================
     //                         Disable Warning Messages
     //===========================================================================
    
    initial begin
    #1ps;         //(any time here should work, as long as it is before the writes)
    sim_tb_top.mem_model_x16.mem.memModels_Ri2[0].memModel2[0].ddr4_model.set_memory_warnings(0,0);
    sim_tb_top.mem_model_x16.mem.memModels_Ri2[0].memModel2[1].ddr4_model.set_memory_warnings(0,0);
    sim_tb_top.mem_model_x16.mem.memModels_Ri2[0].memModel2[2].ddr4_model.set_memory_warnings(0,0);
    sim_tb_top.mem_model_x16.mem.memModels_Ri2[0].memModel2[3].ddr4_model.set_memory_warnings(0,0);
    end

 

Please use this logic to apply it to your application and let me know if you have any issues. To turn the warning messages back on you need to set_memory_warnings(1,1) using the same logic above in your test bench.

 

Thanks,

Cory

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1,466 Views
Registered: ‎09-14-2017

Re: Ultrascale+ DDR4 example design(ies) simulation issue

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Hello, Coryb~

 

Thank you very very much.

It is  working vert well.

I am very appreciate your efforts.

Thanks again.

BR,

 

from yd.je

 

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