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Visitor frac
Visitor
727 Views
Registered: ‎03-07-2018

Ultrascale+ termination for PL DDR4

Is the impedance of the PL DDR drivers fixed, or is it adjustable?

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4 Replies
Moderator
Moderator
706 Views
Registered: ‎04-18-2011

Re: Ultrascale+ termination for PL DDR4

Hi Trac,

I would guess it is fixed by the ip? What seems to be the problem?
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Visitor frac
Visitor
699 Views
Registered: ‎03-07-2018

Re: Ultrascale+ termination for PL DDR4

We're doing a board layout, and our SI analysis is showing that a higher termination impedance would help with the line lengths that we want to use.

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Moderator
Moderator
694 Views
Registered: ‎11-28-2016

Re: Ultrascale+ termination for PL DDR4

Hello @frac,

 

Changing the auto generated IP settings like ODT values or slew rate settings is not supported by Xilinx and could cause post calibration data errors in the field.  Make sure to follow the guidelines in UG583 and if you need to go outside of these guidelines in order to get the best results in your specific application then perform extensive simulations on the interface to make sure the changes you did to the layout are working as intended and the interface is still within specification.  

 

Here's a link to the latest version of UG583:

https://www.xilinx.com/support/documentation/user_guides/ug583-ultrascale-pcb-design.pdf

Visitor frac
Visitor
683 Views
Registered: ‎03-07-2018

Re: Ultrascale+ termination for PL DDR4

Hi @ryana

 

Thanks for the reply. We are following UG583 as best we can, and we are also doing extensive SI analysis on our layout to validate our design.

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