04-27-2018 03:42 PM
04-27-2018 03:47 PM
We're doing a board layout, and our SI analysis is showing that a higher termination impedance would help with the line lengths that we want to use.
04-27-2018 04:13 PM - edited 04-27-2018 04:14 PM
Changing the auto generated IP settings like ODT values or slew rate settings is not supported by Xilinx and could cause post calibration data errors in the field. Make sure to follow the guidelines in UG583 and if you need to go outside of these guidelines in order to get the best results in your specific application then perform extensive simulations on the interface to make sure the changes you did to the layout are working as intended and the interface is still within specification.
Here's a link to the latest version of UG583:
04-27-2018 04:52 PM