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VCU118 DDR4 MIG xdc warning with vivado2016.4: No pins matched

Explorer
Posts: 268
Registered: ‎03-18-2008

VCU118 DDR4 MIG xdc warning with vivado2016.4: No pins matched

set_multicycle_path -setup 8 -from [get_pins */u_ddr_cal_top/calDone*/C]
set_multicycle_path -end -hold 7 -from [get_pins */u_ddr_cal_top/calDone*/C]

set_false_path -hold -to [get_pins */*/*/*/*/*.u_xiphy_control/xiphy_control/RIU_ADDR*]
set_false_path -hold -to [get_pins */*/*/*/*/*.u_xiphy_control/xiphy_control/RIU_WR_DATA*]

set_max_delay 5.0 -datapath_only -from [get_pins */*/*/u_ddr_cal_addr_decode/io_ready_lvl_reg/C] -to [get_pins */u_io_ready_lvl_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 5.0 -datapath_only -from [get_pins */*/*/u_ddr_cal_addr_decode/io_read_data_reg[*]/C] -to [get_pins */u_io_read_data_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 3.0 -datapath_only -from [get_pins */*/*/phy_ready_riuclk_reg/C] -to [get_pins */u_phy2clb_phy_ready_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 3.0 -datapath_only -from [get_pins */*/*/bisc_complete_riuclk_reg/C] -to [get_pins */u_phy2clb_bisc_complete_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 3.0 -datapath_only -from [get_pins */*/io_addr_strobe_lvl_riuclk_reg/C] -to [get_pins */u_io_addr_strobe_lvl_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 3.0 -datapath_only -from [get_pins */*/io_write_strobe_riuclk_reg/C] -to [get_pins */u_io_write_strobe_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 3.0 -datapath_only -from [get_pins */*/io_address_riuclk_reg[*]/C] -to [get_pins */u_io_addr_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 3.0 -datapath_only -from [get_pins */*/io_write_data_riuclk_reg[*]/C] -to [get_pins */u_io_write_data_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 10.0 -datapath_only -from [get_pins */en_vtc_in_reg/C] -to [get_pins */u_en_vtc_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 10.0 -datapath_only -from [get_pins */*/riu2clb_valid_r1_riuclk_reg[*]/C] -to [get_pins */u_riu2clb_valid_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 10.0 -datapath_only -from [get_pins */*/*/phy2clb_fixdly_rdy_low_riuclk_int_reg[*]/C] -to [get_pins */u_phy2clb_fixdly_rdy_low/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 10.0 -datapath_only -from [get_pins */*/*/phy2clb_fixdly_rdy_upp_riuclk_int_reg[*]/C] -to [get_pins */u_phy2clb_fixdly_rdy_upp/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 10.0 -datapath_only -from [get_pins */*/*/phy2clb_phy_rdy_low_riuclk_int_reg[*]/C] -to [get_pins */u_phy2clb_phy_rdy_low/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 10.0 -datapath_only -from [get_pins */*/*/phy2clb_phy_rdy_upp_riuclk_int_reg[*]/C] -to [get_pins */u_phy2clb_phy_rdy_upp/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 10.0 -datapath_only -from [get_pins */rst_r1_reg/C] -to [get_pins */u_fab_rst_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 3.0 -datapath_only -from [get_pins  */*/*/clb2phy_t_b_addr_riuclk_reg/C] -to [get_pins  */*/*/clb2phy_t_b_addr_i_reg[0]/D]
set_max_delay 3.0 -datapath_only -from [get_pins  */*/*/*/slave_en_lvl_reg/C] -to [get_pins  */*/*/*/u_slave_en_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 3.0 -datapath_only -from [get_pins  */*/*/*/slave_we_r_reg/C] -to [get_pins  */*/*/*/u_slave_we_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 3.0 -datapath_only -from [get_pins  */*/*/*/slave_addr_r_reg[*]/C] -to [get_pins  */*/*/*/u_slave_addr_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 3.0 -datapath_only -from [get_pins  */*/*/*/slave_di_r_reg[*]/C] -to [get_pins  */*/*/*/u_slave_di_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 3.0 -datapath_only -from [get_pins  */*/*/*/slave_rdy_cptd_sclk_reg/C] -to [get_pins  */*/*/*/u_slave_rdy_cptd_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 12.0 -datapath_only -from [get_pins */*/*/*/slave_rdy_lvl_fclk_reg/C] -to [get_pins  */*/*/*/u_slave_rdy_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 12.0 -datapath_only -from [get_pins */*/*/*/slave_do_fclk_reg[*]/C] -to [get_pins  */*/*/*/u_slave_do_sync/SYNC[*].sync_reg_reg[0]/D]
set_false_path -through [get_pins u_ddr4_infrastructure/sys_rst]
set_false_path -from [get_pins  */input_rst_design_reg/C] -to [get_pins */rst_div_sync_r_reg[0]/D]
set_false_path -from [get_pins  */input_rst_design_reg/C] -to [get_pins */rst_riu_sync_r_reg[0]/D]
set_false_path -from [get_pins  */input_rst_design_reg/C] -to [get_pins */rst_mb_sync_r_reg[0]/D]
set_false_path -from [get_pins  */rst_async_riu_div_reg/C] -to [get_pins */rst_div_sync_r_reg[0]/D]
set_false_path -from [get_pins  */rst_async_mb_reg/C]      -to [get_pins */rst_mb_sync_r_reg[0]/D]
set_false_path -from [get_pins  */rst_async_riu_div_reg/C] -to [get_pins */rst_riu_sync_r_reg[0]/D]

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WARNING: [Vivado 12-508] No pins matched '*/u_ddr_cal_top/calDone*/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:257]
CRITICAL WARNING: [Vivado 12-4739] set_multicycle_path:No valid object(s) found for '-from [get_pins */u_ddr_cal_top/calDone*/C]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:257]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/u_ddr_cal_top/calDone*/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:258]
CRITICAL WARNING: [Vivado 12-4739] set_multicycle_path:No valid object(s) found for '-from [get_pins */u_ddr_cal_top/calDone*/C]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:258]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/*/*/*/*/*.u_xiphy_control/xiphy_control/RIU_ADDR*'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:265]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_pins */*/*/*/*/*.u_xiphy_control/xiphy_control/RIU_ADDR*]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:265]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/*/*/*/*/*.u_xiphy_control/xiphy_control/RIU_WR_DATA*'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:266]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_pins */*/*/*/*/*.u_xiphy_control/xiphy_control/RIU_WR_DATA*]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:266]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/*/*/u_ddr_cal_addr_decode/io_ready_lvl_reg/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:285]
WARNING: [Vivado 12-508] No pins matched '*/u_io_ready_lvl_sync/SYNC[*].sync_reg_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:285]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_pins */*/*/u_ddr_cal_addr_decode/io_ready_lvl_reg/C]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:285]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/*/*/u_ddr_cal_addr_decode/io_read_data_reg[*]/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:286]
WARNING: [Vivado 12-508] No pins matched '*/u_io_read_data_sync/SYNC[*].sync_reg_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:286]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_pins {*/*/*/u_ddr_cal_addr_decode/io_read_data_reg[*]/C}]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:286]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/*/*/phy_ready_riuclk_reg/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:287]
WARNING: [Vivado 12-508] No pins matched '*/u_phy2clb_phy_ready_sync/SYNC[*].sync_reg_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:287]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_pins */*/*/phy_ready_riuclk_reg/C]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:287]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/*/*/bisc_complete_riuclk_reg/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:288]
WARNING: [Vivado 12-508] No pins matched '*/u_phy2clb_bisc_complete_sync/SYNC[*].sync_reg_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:288]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_pins */*/*/bisc_complete_riuclk_reg/C]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:288]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/*/io_addr_strobe_lvl_riuclk_reg/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:289]
WARNING: [Vivado 12-508] No pins matched '*/u_io_addr_strobe_lvl_sync/SYNC[*].sync_reg_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:289]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_pins */*/io_addr_strobe_lvl_riuclk_reg/C]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:289]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/*/io_write_strobe_riuclk_reg/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:290]
WARNING: [Vivado 12-508] No pins matched '*/u_io_write_strobe_sync/SYNC[*].sync_reg_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:290]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_pins */*/io_write_strobe_riuclk_reg/C]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:290]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/*/io_address_riuclk_reg[*]/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:291]
WARNING: [Vivado 12-508] No pins matched '*/u_io_addr_sync/SYNC[*].sync_reg_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:291]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_pins {*/*/io_address_riuclk_reg[*]/C}]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:291]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/*/io_write_data_riuclk_reg[*]/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:292]
WARNING: [Vivado 12-508] No pins matched '*/u_io_write_data_sync/SYNC[*].sync_reg_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:292]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_pins {*/*/io_write_data_riuclk_reg[*]/C}]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:292]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/en_vtc_in_reg/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:293]
WARNING: [Vivado 12-508] No pins matched '*/u_en_vtc_sync/SYNC[*].sync_reg_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:293]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_pins */en_vtc_in_reg/C]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:293]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/*/riu2clb_valid_r1_riuclk_reg[*]/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:294]
WARNING: [Vivado 12-508] No pins matched '*/u_riu2clb_valid_sync/SYNC[*].sync_reg_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:294]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_pins {*/*/riu2clb_valid_r1_riuclk_reg[*]/C}]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:294]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/*/*/phy2clb_fixdly_rdy_low_riuclk_int_reg[*]/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:295]
WARNING: [Vivado 12-508] No pins matched '*/u_phy2clb_fixdly_rdy_low/SYNC[*].sync_reg_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:295]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_pins {*/*/*/phy2clb_fixdly_rdy_low_riuclk_int_reg[*]/C}]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:295]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/*/*/phy2clb_fixdly_rdy_upp_riuclk_int_reg[*]/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:296]
WARNING: [Vivado 12-508] No pins matched '*/u_phy2clb_fixdly_rdy_upp/SYNC[*].sync_reg_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:296]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_pins {*/*/*/phy2clb_fixdly_rdy_upp_riuclk_int_reg[*]/C}]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:296]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/*/*/phy2clb_phy_rdy_low_riuclk_int_reg[*]/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:297]
WARNING: [Vivado 12-508] No pins matched '*/u_phy2clb_phy_rdy_low/SYNC[*].sync_reg_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:297]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_pins {*/*/*/phy2clb_phy_rdy_low_riuclk_int_reg[*]/C}]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:297]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/*/*/phy2clb_phy_rdy_upp_riuclk_int_reg[*]/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:298]
WARNING: [Vivado 12-508] No pins matched '*/u_phy2clb_phy_rdy_upp/SYNC[*].sync_reg_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:298]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_pins {*/*/*/phy2clb_phy_rdy_upp_riuclk_int_reg[*]/C}]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:298]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/rst_r1_reg/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:299]
WARNING: [Vivado 12-508] No pins matched '*/u_fab_rst_sync/SYNC[*].sync_reg_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:299]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_pins */rst_r1_reg/C]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:299]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/*/*/clb2phy_t_b_addr_riuclk_reg/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:300]
WARNING: [Vivado 12-508] No pins matched '*/*/*/clb2phy_t_b_addr_i_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:300]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_pins */*/*/clb2phy_t_b_addr_riuclk_reg/C]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:300]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/*/*/*/slave_en_lvl_reg/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:301]
WARNING: [Vivado 12-508] No pins matched '*/*/*/*/u_slave_en_sync/SYNC[*].sync_reg_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:301]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_pins */*/*/*/slave_en_lvl_reg/C]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:301]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/*/*/*/slave_we_r_reg/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:302]
WARNING: [Vivado 12-508] No pins matched '*/*/*/*/u_slave_we_sync/SYNC[*].sync_reg_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:302]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_pins */*/*/*/slave_we_r_reg/C]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:302]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/*/*/*/slave_addr_r_reg[*]/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:303]
WARNING: [Vivado 12-508] No pins matched '*/*/*/*/u_slave_addr_sync/SYNC[*].sync_reg_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:303]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_pins {*/*/*/*/slave_addr_r_reg[*]/C}]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:303]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/*/*/*/slave_di_r_reg[*]/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:304]
WARNING: [Vivado 12-508] No pins matched '*/*/*/*/u_slave_di_sync/SYNC[*].sync_reg_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:304]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_pins {*/*/*/*/slave_di_r_reg[*]/C}]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:304]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/*/*/*/slave_rdy_cptd_sclk_reg/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:305]
WARNING: [Vivado 12-508] No pins matched '*/*/*/*/u_slave_rdy_cptd_sync/SYNC[*].sync_reg_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:305]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_pins */*/*/*/slave_rdy_cptd_sclk_reg/C]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:305]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/*/*/*/slave_rdy_lvl_fclk_reg/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:306]
WARNING: [Vivado 12-508] No pins matched '*/*/*/*/u_slave_rdy_sync/SYNC[*].sync_reg_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:306]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_pins */*/*/*/slave_rdy_lvl_fclk_reg/C]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:306]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/*/*/*/slave_do_fclk_reg[*]/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:307]
WARNING: [Vivado 12-508] No pins matched '*/*/*/*/u_slave_do_sync/SYNC[*].sync_reg_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:307]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_pins {*/*/*/*/slave_do_fclk_reg[*]/C}]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:307]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched 'u_ddr4_infrastructure/sys_rst'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:308]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-through [get_pins u_ddr4_infrastructure/sys_rst]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:308]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/input_rst_design_reg/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:309]
WARNING: [Vivado 12-508] No pins matched '*/rst_div_sync_r_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:309]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_pins */input_rst_design_reg/C]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:309]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/input_rst_design_reg/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:310]
WARNING: [Vivado 12-508] No pins matched '*/rst_riu_sync_r_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:310]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_pins */input_rst_design_reg/C]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:310]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/input_rst_design_reg/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:311]
WARNING: [Vivado 12-508] No pins matched '*/rst_mb_sync_r_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:311]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_pins */input_rst_design_reg/C]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:311]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/rst_async_riu_div_reg/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:312]
WARNING: [Vivado 12-508] No pins matched '*/rst_div_sync_r_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:312]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_pins */rst_async_riu_div_reg/C]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:312]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/rst_async_mb_reg/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:313]
WARNING: [Vivado 12-508] No pins matched '*/rst_mb_sync_r_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:313]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_pins */rst_async_mb_reg/C]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:313]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched '*/rst_async_riu_div_reg/C'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:314]
WARNING: [Vivado 12-508] No pins matched '*/rst_riu_sync_r_reg[0]/D'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:314]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_pins */rst_async_riu_div_reg/C]'. [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc:314]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
Finished Parsing XDC File [e://xilinx_vcu118_ip/xilinx_vcu118_ip/xilinx_vcu118_ip.srcs/sources_1/ip/ddr4_1/par/ddr4_1.xdc]

Highlighted
Moderator
Posts: 5,204
Registered: ‎09-20-2012

Re: VCU118 DDR4 MIG xdc warning with vivado2016.4: No pins matched

Hi @m006

 

Are you still seeing this issue?

 

What flow are you using? 

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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