XCKU5P-1FFVB676 DDR3 Modules

[alex83uk]

Hi all, my question is similar to this one here.

Can I have an XCKU5P-1FFVB676 with four 16bits DDR3 Modules? If so, how can I find out which pins connect to what?

Thanks in advance!

[alex83uk]

I've got an update on this.

I've found this link on this page and apparently yes, I can have four DDR3 16bits <=512M.

Now the only question is, how can I find out which pins I can connect the modules to?

[jg_bds]

You're going to have to fire-up Vivado and start flinging MIG IPs* into a block diagram--to see where you can place DDR pins. They'll likely go in the 4 HP banks that exist in your chip, but you'll have to go through the whole FPGA-design process to ascertain exact pin locations.

-Joe G.

*Sadly, the Ultrascale MIG only allows you to create one controller at a time (S7 MIG lets you create up to 4 in one IP), so you'll need to configure one and then replicate it 3 more times.

[alex83uk]

Thank you for replying @jg_bds

I've created a Vivado project and added one DDR3 (MIG). I'm now trying to open the I/O Planning environment by clicking on 'Open Elaborated Design' but I get an error since I don't have a Top module. Is there a way around it? I don't have any code written yet, I just want to make sure that it is actually possible to have four DDRs and which pins I can connect them to.

This video here shows what I would like to accomplish, but unfortunately they have changed the MIG IP so it's not that simple anymore.

[jg_bds · Accepted solution]

The design flow for the MIG has changed a lot since that video was made.  Expect bumps in the road.

If you're using the "Example Design" flow from the video and not using IP Integrator, it's going to be difficult to get more than one controller instantiated.  If you still want to follow that flow, go back to @8:45 of the video to see the step you missed (Open IP Example Design...). You need to open that new project in order to proceed through implementation.

The flow I'd recommend is using IPI to create a block diagram. Place one MIG IP and then configure it for your memory set-up. Then copy and paste that IP 3 more times. You can use the block diagram I created in the post you referenced above (cramming 4 DDR interfaces into an S7 FPGA) as a guide to get a complete design with all 4 controllers that you can carry all the way through implementation.

The core of your BD, however, will be 4 separate MIGs, rather than a single, 4-controller MIG:

-Joe G.

[alex83uk]

Hello @jg_bds Thank you for replying.

I've tried the flow you recommended and I believe I'm almost there, but Vivado is getting stuck on something. I've done the block diagram below, and when I click on 'Open Elaborated Design' the program gets stuck on 'Running design_1_ddr3_1_0_synth_1'. On my Tcl Console I get 'Waiting for design_1_ddr3_1_0_synth_1 to finish...' every few seconds. Please note that I didn't place the clock buffers as you did on your other post.

[jg_bds]

To be honest, I haven't built an US/US+ MIG since 2017.4.  When I tried to synthesize in 18.2, Vivado soiled the sheets.  I upgraded to 18.3, and was able to get through synthesis.

What version are you using?

-Joe G.

[alex83uk]

I'm using Vivado 18.3.

I've swapped the AXI SmartConnect to AXI Interconnect as your latest block diagram and now the design gets through synthesis/implementation. Thank you!

Now the question is, how can I see which net is connected to which package pin? When I click on 'Open Elaborated Design' it shows me only one DDR device, not four.

[jg_bds]

Well, nothing's connected to an FPGA pin until you connect it.

After Synth completes, open the Synthesized design. Do Menu Bar -> Tools -> I/O Planning -> Memory Byte Planner to rough-assign the memory bytes of the DDR interfaces.

After that, if you don't see the I/O Ports tab on the bottom part of the screen, do Menu Bar -> Layout -> I/O Planning.

Go through all of the ports and make sure all of the assignments look ok.  Also assign any of the other, unassigned design ports.

After that's done, save and then proceed with Implementation.

-Joe G.

P.S.  Make sure the I/O Std of the DDR Reset signals are all set to LVCMOS15, not SSTL15.

[alex83uk]

Oh I see, I thought they would be auto-assigned.

After synth completes, when I click on the Memory Byte Planner, I can only see one DDR. Why are the other 3 missing?

[jg_bds]

Dunno.

If you ran Synth with all 4 MIG's, they should be there.

-Joe G.

P.S.  Assign the 2 data bytes and leave-off Add/Ctrl-2. There will be fewer ports to assign manually.

[alex83uk]

Hmm.. All 4 MIGs are there. My block diagram is the same as yours.

Would you mind sharing this project you are running? I'd like to check what the differences are.

[jg_bds]

Here you go.

-Joe G.

[alex83uk]

Thanks a million @jg_bds !!!!! That's exactly what I was trying to do.

P.S.: I still don't know why my design only showed a single DDR since our block diagrams are identical.