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Visitor tijanai
Visitor
128 Views
Registered: ‎01-18-2019

XZCU15EG DDR3L Timing Parameters

 

Hello,

For the Zynq Ultra Scale Plus 15EG, are there any DDR3L timing parameters available for the controller?

I’ve been looking for the address/command/control set and hold times with respect to the DDR_CLK, the DWS skew with respect to the CLK, and the DW skew with respect to DQS. I have yet to find anything within the documentation. Unsure if this means we will have to get them from the Xilinx tools.

Thanks,

Tijana

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1 Reply
Moderator
Moderator
85 Views
Registered: ‎11-28-2016

Re: XZCU15EG DDR3L Timing Parameters

Hello @tijanai,

The information you're looking for can be found in the UltraScale+ Signal and Power Integrity lounge under the HyperLynx DDRx Wizard Models tab.  Here's a link and you'll have to request access:
https://www.xilinx.com/member/ultrascaleplus_si_pi_lounge.html#HyperLynx