06-11-2018 01:47 PM
I am using PL DDR4 (MIG) on zcu106 board. The configuration of ddr4 (MIG) is based on board preset. But after synthesis, I got critical warning, it complains that some of ddr4 ports cannot be assign pins based on the preset. The message is showing below:
I open the i/o planning and try to set pins for these ports manually based on the board doc, but it does not allow me to set specific pins for these ports. The message is showing below:
Does anyone know about this?
06-13-2018 09:22 AM
I did not receive any critical warnings in Vivado 2018.1 while using the ddr_sdram preset. Can you please try using the below settings in your IP, then building the IP Example Design to see if you still run into the issue?
06-18-2018 06:31 AM - edited 06-20-2018 08:29 AM
06-20-2018 09:47 AM
I have sent you an EZmove package with the testcase / example design I used for 2018.1 / ZCU106. Please test it our on your end.
06-20-2018 02:29 PM
06-20-2018 02:41 PM
You should not have any MIG constraints in the top level XDC if you are using the board presets for MIG. What constraints do you have leading to your issue?
06-21-2018 06:35 AM - edited 06-21-2018 06:37 AM