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Zynq UltraScale+ x64 LPDDR3 support in PL

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Visitor
Posts: 1
Registered: ‎05-16-2018
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Zynq UltraScale+ x64 LPDDR3 support in PL

I have a question regarding the Zynq UltraScale+ MPSoC and LPDDR3 support on the PL side.

 

The LPDDR3 controller IP overview indicates x64 device targets. However, PG150 shows only x32 device support. Additionally, at the following link there is no mention of support for LPDDR3 on the Programmable Logic Memory Solutions section for these devices.

 

https://www.xilinx.com/products/technology/memory.html#overview

 

 

 

I want to confirm that it appears there is really only support for LPDDR3 (x32 & x64) on the PS side and there is minimal support (x32) if any for LPDDR3 on the PL side.

 


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Xilinx Employee
Posts: 191
Registered: ‎11-28-2016

Re: Zynq UltraScale+ x64 LPDDR3 support in PL

[ Edited ]

Hello @cataclysm10,

 

In the Feature Summary section of the LPDDR3 documentation in PG150 starting on page 259 you'll see that the PL can only support x32 devices. Note that the PL only supports single rank, single placement, and single die components.  There's a link to PG150 in my signature.

 

In Table 17-2 Example Memory Configurations on page 430 of UG1085 for the Zynq UltraScale+ MPSoC PS memory interfaces you'll see that the IP can support two placements of x32 devices for a total of a 64-bit wide interface.

https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf

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Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

PG150 - UltraScale Memory Product Guide

UG583 - UltraScale Architecture PCB Design User Guide

UG586 - 7 Series FPGAs Memory Interface Solution User Guide

DDR3 and DDR4 Memory Interface Calibration and Hardware Debug Guide

View solution in original post


All Replies
Xilinx Employee
Posts: 191
Registered: ‎11-28-2016

Re: Zynq UltraScale+ x64 LPDDR3 support in PL

[ Edited ]

Hello @cataclysm10,

 

In the Feature Summary section of the LPDDR3 documentation in PG150 starting on page 259 you'll see that the PL can only support x32 devices. Note that the PL only supports single rank, single placement, and single die components.  There's a link to PG150 in my signature.

 

In Table 17-2 Example Memory Configurations on page 430 of UG1085 for the Zynq UltraScale+ MPSoC PS memory interfaces you'll see that the IP can support two placements of x32 devices for a total of a 64-bit wide interface.

https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

PG150 - UltraScale Memory Product Guide

UG583 - UltraScale Architecture PCB Design User Guide

UG586 - 7 Series FPGAs Memory Interface Solution User Guide

DDR3 and DDR4 Memory Interface Calibration and Hardware Debug Guide