Thank you for taking the time to read this and answer.
We are laying out a new design using the Zynq Ultrascale+ XCZU3CG-1SFVA625c. Currently we have the DDR4 DRAM laid out as per UG583 using fly-by topology. We matched the length as per the requirements on UG583 and also used the package flight times from Vivado for the XCZU3CG-1SFVA625 package.
Now we have a question regarding the General Memory Routing Guidelines item #6 where the CK clock is related to the DQS/DQ Data byte lanes. We just have 2 DDR4 DRAM devices we are routing too. We have the CK going to the first device and the DQS/DQ byte lane 1 is 300ps shorter than the CK and the DQS/DQ byte lane 2 is shorter than the CK by about 200ps. Not on the second device the CK clock hits the DQS/DQ byte lane 2 is just 100ps shorter and the DQS/DQ byte lane 3 is just 125ps shorter. So the question pertains to the figure 2-7. It seems to show that the first device the CK clock hits the DQS/DQ byte lanes should have less of a skew in relation to the CK signal than the second device the CK clock line goes too. In our case the skew is shorter going to the second device than the first device. Is this a problem or does write level compensate for that.
Note we also did not do any bit swapping in the DQS/DQ byte lanes which may have made the traces longer than if we did.
Please let me know if I am ok with this layout.
As you well know, ANY difference from what is recommended is an unknown: don't do it.
If the SI CAD tool is reporting the skews you see, I would go back and have the layout changed.
Example layouts do exist for our boards (example ZCU102), so I would also look at what we do.
Thank you for the quick reply.
So what I was asking from the above question, is it true that the first device the CK clock hits the DQS/DQ byte lanes should have less skew in relation to the CK than the second device or does it matter? This is not clear from to the figure 2-7.
Thank you again,
Using the clock pin as reference in 2-7, the first device DQS should not be less than -149 ps (no earlier), and the last device DQS should be no later than +1796. The delay of the clock is assumed to be less to get to the first device, and is only greater to get to second device. So clock routing could go to second first, the first. The -149 and 1796 still apply (to first and second).
Does that make sense?
I am the PCB designer that is working with Gary. If we change the order of the route for the CLK lines, will there ban any effects to the address bus? The address, command, control and clk lines were routed to DDR4 device 1 and then to DDR4 device 2.
Obviously ALL requirements need to be met. So, routing the clock 'backwards' only matters if it changes the clock arrival time to the part in such a way that violates another requirement.
So, I am not verifying your layout. I am commenting on questions, interpretation of the requirements. If you want approval of your layout, you may request such from your local distributor, through their sales office. It becomes more than a question of opinion, and becomes a paid service, as no one will guarantee your board will work unless they have the tools, and means to provide sufficient simulation, verification, SI CAD tools, engineering skills to do so. Even so, I have seen boards with mistakes requiring re-spins. The best you can do is to use a layout known to work. Next best is to follow our guidelines to the letter. Deviation from our suggestions takes you into you being on your own to verify it works, and accepting the risk.
If you can get a review of your layout for free that you trust, then go for it. The more eyes than review it that understand what is needed, is only goodness.
Thank you for the information. Should we have to take into account the trace length from the last device to the termination resistors? I believe we should, however, I have not found anything in the UG583 document. I may have missed it.
Signal Integrity analysis,
Is required on all traces. Unless you followed a proven working layout exactly.