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app_rdy and app_wdf_rdy signals is at low

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Adventurer
Posts: 66
Registered: ‎12-05-2016
Accepted Solution

app_rdy and app_wdf_rdy signals is at low

hi all,

i am using MIG in my design. but when i programmed it to the KC705 board and checked using ILA core the app_rdy and app_wdf_rdy signals found to be low. for writing data to DDR it should go high, right? what can be the reason ?

one more thing the sys_clk_p  and sys_clk_n signals are mapped to the pins AH6 and AH7. clock frequency is set at 200mhz. from the ip source's xdc i found the following lines;

create_clock -period 5 [get_ports sys_clk_p]

set_property VCCAUX_IO DONTCARE [get_ports {sys_clk_p}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {sys_clk_p}]
set_property PACKAGE_PIN AH6 [get_ports {sys_clk_p}]

# PadFunction: IO_L14N_T2_SRCC_34
set_property VCCAUX_IO DONTCARE [get_ports {sys_clk_n}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {sys_clk_n}]
set_property PACKAGE_PIN AH5 [get_ports {sys_clk_n}]

what does it means? will it creates the clock by itself?

 

thanks in advance,

regards,

Reshma


Accepted Solutions
Moderator
Posts: 5,330
Registered: ‎09-20-2012

Re: app_rdy and app_wdf_rdy signals is at low

[ Edited ]

Hi @reshmaakhil

 

XTP uses AD11/AD12 for system clock which is connected to 200Mhz oscillator.

 

The same 200Mhz (5000ps) is selected for "input clock period" in XTP. 

 

Are you setting this "input clock period" to different value?

 

You cannot use AH6 for sys_clk_p as this is not connected to oscillator (its connected to DQ pin of memory). Refer to Table 1-4 in https://www.xilinx.com/support/documentation/boards_and_kits/kc705/ug810_KC705_Eval_Bd.pdf

Thanks,
Deepika.
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Moderator
Posts: 5,330
Registered: ‎09-20-2012

Re: app_rdy and app_wdf_rdy signals is at low

[ Edited ]

Hi @reshmaakhil

 

The sys_clk IP input port should be locked to package pin which is connected to oscillator on board.

 

What is the status of init_calib_complete signal? This should be high.

 

Follow the instructions in XTP196 to generate MIG IP, you can download the XTP doc here https://secure.xilinx.com/webreg/login.do?oamProtectedResource=wh%3Dwww.xilinx.com%20wu%3D%2Fwebreg%2Fclickthrough.do%3Fcid%3D370263%26license%3DRefDesLicense%26filename%3Dxtp196-kc705-mig-c-2014-3.pdf%26languageID%3D1%20wo%3D1%20rh%3Dhttps%3A%2F%2Fs...

 

You can find XTP file here https://secure.xilinx.com/webreg/login.do?oamProtectedResource=wh%3Dwww.xilinx.com%20wu%3D%2Fwebreg%2Fclickthrough.do%3Fcid%3D370268%26license%3DRefDesLicense%26filename%3Drdf0186-kc705-mig-c-2014-3.zip%26languageID%3D1%20wo%3D1%20rh%3Dhttps%3A%2F%2F...

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
Adventurer
Posts: 66
Registered: ‎12-05-2016

Re: app_rdy and app_wdf_rdy signals is at low

hi @vemulad

 the oscillator output clock frequency was not matching with the selected mig frequency. thats why i didnt connect like that. my init_calib_complete signal was unconnected. i will connect it and inform the result asap.

Regards,

Reshma

Moderator
Posts: 5,330
Registered: ‎09-20-2012

Re: app_rdy and app_wdf_rdy signals is at low

[ Edited ]

Hi @reshmaakhil

 

XTP uses AD11/AD12 for system clock which is connected to 200Mhz oscillator.

 

The same 200Mhz (5000ps) is selected for "input clock period" in XTP. 

 

Are you setting this "input clock period" to different value?

 

You cannot use AH6 for sys_clk_p as this is not connected to oscillator (its connected to DQ pin of memory). Refer to Table 1-4 in https://www.xilinx.com/support/documentation/boards_and_kits/kc705/ug810_KC705_Eval_Bd.pdf

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
Adventurer
Posts: 66
Registered: ‎12-05-2016

Re: app_rdy and app_wdf_rdy signals is at low

ok, i understood the mistake. i will modify it and send the result. thanks a lot for your support
Adventurer
Posts: 66
Registered: ‎12-05-2016

Re: app_rdy and app_wdf_rdy signals is at low

hi, 

it is showing one error;

[DRC 23-20] Rule violation (RTRES-1) Backbone resources - 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources. The problem net(s) are cmp2/u_mig_7series_0_mig/u_ddr3_clk_ibuf/sys_clk_ibufg.

can i use the same steps in the following link?

 

https://forums.xilinx.com/t5/Memory-Interfaces/CLOCK-DEDICATED-ROUTE-set-to-BACKBONE/m-p/741005#M10171

 

regards,

Reshma

Moderator
Posts: 5,330
Registered: ‎09-20-2012

Re: app_rdy and app_wdf_rdy signals is at low

Hi @reshmaakhil

 

What pins did you choose for system clock during IP customization?

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
Moderator
Posts: 5,330
Registered: ‎09-20-2012

Re: app_rdy and app_wdf_rdy signals is at low

Hi @reshmaakhil

 

Please close the thread by marking the answer if your query is addressed.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
Adventurer
Posts: 66
Registered: ‎12-05-2016

Re: app_rdy and app_wdf_rdy signals is at low

hi @vemulad,

thanks for the support. now its clear, i was able to generate the bit stream successfully. 

regards,

Reshma