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Adventurer
Adventurer
813 Views
Registered: ‎04-21-2018

app_rdy continous data

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Hi,

 

I have a flow of continuous data coming to my FPGA and i want to store it in the DDR 3 memory.

I have been simulating the Memory Controller but after the first write command i see that the signal app_rdy goes low.

My problem is that my data is coming continuously and in theory i can't wait for app_rdy to go back high to write on the DDR3 memory.

Is the behaviour of app_rdy predictable? Is it normal that it goes low after only one write command?

 

Here is a wave of my simulation

Thanks

wave1.png
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1 Solution

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Moderator
Moderator
999 Views
Registered: ‎02-11-2014

Re: app_rdy continous data

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Hello @mildredhayes,

 

I am not 100% but the bad data could be coming from an undefined app_wdf_mask. I would suggest tying your app_wdf_mask signal to 0 if you don't plan on using it. And in HW, tie DM to ground if you don't plan on using it.

 

Are you only seeing this issue in simulation or is it also happening in HW too?

 

Thanks,

Cory

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Moderator
Moderator
744 Views
Registered: ‎02-11-2014

Re: app_rdy continous data

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Hello @mildredhayes,

 

I would have to see your test bench/traffic generator to fully understand what you are doing. But basically you need to setup some logic to wait for app_rdy to assert again before sending more data. Our IP Example Design does a pretty good job our outlining this for you, based around your IP configuration. It would also be good to see what type of ordering and address map you are doing as well. That can effect efficiency.

 

Thanks,

Cory

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Adventurer
Adventurer
729 Views
Registered: ‎04-21-2018

Re: app_rdy continous data

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Thanks, what do you mean by setup some logic to wait for app_rdy?

What i do in my traffic generator is the following:

I'm testing a memory controller using the MIG of VIVADO., I configured the memory controller the following way:

  • Controller Type: DDR3 SDRAM
  • Clock Period: 1250 ps 800 MHz
  • PHY to controller ratio 4:1
  • Memory Type:SODIMMs
  • Data Width: 64
  • Number of Bank Machines: 4
  • Input clock period for the PLL: 5000 ps 200 MHz
  • Read burst type and length : Sequential
  • Memory Address Mapping Selection: BANK/ROW/COLUMN

I have modified the xilinx testbench example. This is what happens in my test bench.

I wait for init_calib_complete to rise to '1' Then when app_rdy = '1' and app_wdf_rdy = '1', I set

  • app_en to '1' for one ui_clk cycle
  • app_cmd to "000" (write command)
  • app_wdf_data to 100000....000 (512 bits)
  • app_add to "000..00" (27 bits)

Then after this write command I issue a read command on the same address. And when app_rd_data_valid rises to '1', I see that app_rd_data = "1c2c57..." (512 bits) while I was expecting to read "100000....000" (512 bits).

Here is a wave of my simulation. Appart of the app_rdy I don't really understand why the value that I read is totally different from the one I wrote on the same address.

simulationwave.png
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Moderator
Moderator
1,000 Views
Registered: ‎02-11-2014

Re: app_rdy continous data

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Hello @mildredhayes,

 

I am not 100% but the bad data could be coming from an undefined app_wdf_mask. I would suggest tying your app_wdf_mask signal to 0 if you don't plan on using it. And in HW, tie DM to ground if you don't plan on using it.

 

Are you only seeing this issue in simulation or is it also happening in HW too?

 

Thanks,

Cory

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Adventurer
Adventurer
689 Views
Registered: ‎04-21-2018

Re: app_rdy continous data

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That was exactly the issue, the app_wdf_mask was undefined.

Thank you very much! The simulation works now. (I am not doing the HW test for the moment)

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