01-19-2017 12:03 AM
i am doing my vivado project in KC705 board. I am using both MIG and pcie. pcie side is working and i am getting data through pcie(verified using ILA core). but my MIG interface is not properly working. app_wdf_rdy signal is high but app_rdy is low. i mapped init_calib_complete to one led, but it is not glowing. can anyone help me? please.
mig ipcore details attached.
Thanks in advance.
01-19-2017 12:20 AM
01-19-2017 12:24 AM
thanks for your reply.
I already completed the steps mentioned in the post
after that only i was able complete bit stream generation. and now the app_wdf_rdy signal is high. problem is with the other one.
01-19-2017 12:27 AM
01-19-2017 01:09 AM - edited 01-19-2017 01:22 AM
The app_rdy might be low as calibration is not successful i.e., init_calib_complete is low.
Are you using KC705 board or custom board?
Please do the general checks mentioned in page-232 of UG586 https://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v4_1/ug586_7Series_MIS.pdf .
Also identify which stage of calibration is failing by following steps in page-235 of UG586 https://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v4_1/ug586_7Series_MIS.pdf
01-23-2017 06:16 AM
Did you try the step by step procedure as mentioned in below doc
Do you see init_calib staying low with ready to download bit files provided with the MIG reference design from below link.