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app_rdy signal is at low

Observer
Posts: 59
Registered: ‎12-05-2016

app_rdy signal is at low

hi all,

i am doing my vivado project in KC705 board. I am using both MIG and pcie. pcie side is working and i am getting data through pcie(verified using ILA core). but my MIG interface is not properly working. app_wdf_rdy signal is high but app_rdy is low. i mapped init_calib_complete to one led, but it is not glowing. can anyone help me? please.

mig ipcore details attached.

Thanks in advance. 

Regards,

Reshma

Moderator
Posts: 4,610
Registered: ‎08-01-2008

Re: app_rdy signal is at low

check this post and follow suggestions
https://forums.xilinx.com/t5/Memory-Interfaces/app-rdy-and-app-wdf-rdy-signals-is-at-low/m-p/741943
Thanks and Regards
Balkrishan
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Observer
Posts: 59
Registered: ‎12-05-2016

Re: app_rdy signal is at low

hi @balkris,

thanks for your reply.

I already completed the steps mentioned in the post

https://forums.xilinx.com/t5/Memory-Interfaces/app-rdy-and-app-wdf-rdy-signals-is-at-low/m-p/741943

after that only i was able complete bit stream generation. and now the app_wdf_rdy signal is high. problem is with the other one.

Regards,

Reshma

Moderator
Posts: 4,610
Registered: ‎08-01-2008

Re: app_rdy signal is at low

Please check blow links for app_rdy low reasons



http://www.xilinx.com/support/answers/36719.html



http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/MIG-7-series-Gap-in-continuous-write-read/td-p/365643



http://www.xilinx.com/support/answers/56276.html





If you notice any specific scenario of unexpected app_rdy low periods then please elaborate and share the waveforms
Thanks and Regards
Balkrishan
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Moderator
Posts: 5,204
Registered: ‎09-20-2012

Re: app_rdy signal is at low

[ Edited ]

Hi @reshmaakhil

 

The app_rdy might be low as calibration is not successful i.e., init_calib_complete is low. 

 

Are you using KC705 board or custom board? 

 

Please do the general checks mentioned in page-232 of UG586 https://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v4_1/ug586_7Series_MIS.pdf

 

Also identify which stage of calibration is failing by following steps in page-235 of UG586 https://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v4_1/ug586_7Series_MIS.pdf 

Thanks,
Deepika.
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Observer
Posts: 59
Registered: ‎12-05-2016

Re: app_rdy signal is at low

hi ,
i am using normal KC705 board.
does "init_calib_complete " low indicate a hardware issue?
please do reply. Thanks in advance.
Regards,
Reshma
Moderator
Posts: 2,977
Registered: ‎02-06-2013

Re: app_rdy signal is at low

Hi

 

Did you try the step by step procedure as mentioned in below doc

 

https://www.xilinx.com/support/documentation/boards_and_kits/kc705/2014_3/xtp196-kc705-mig-c-2014-3.pdf

 

Do you see init_calib staying low with ready to download bit files provided with the MIG reference design from below link.

 

https://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html#documentation

 

Regards,

Satish

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