We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Registered: ‎04-11-2016

clock out setting in mig 7 series and routing error


I need clock out from mig (clock 0, clock 1, ....clock 4) as in attachment which is taken from xapp1199.


but when I generate new mig with the same setting as Xapp1199 the clock out part doesn't appear. see both screenshots.

What need to be done for this?


Another thing I have one differential 200 MHZ system clock on KC705 board. But in another design I need 2 input differential clocks and when I give the same clock at 2 input points (one with mig and other as system clock) then vivado shows error as they are dedicated and can not be routed.


Therefore I am thinking to take out clock from mig and convert it into differential using IOBUF and use it differential system clock at another point. Is this method correct? or there is some another way to do it?

Screenshot from 2018-03-28 08-50-33.png
Screenshot from 2018-03-28 08-56-51.png
0 Kudos
1 Reply
Registered: ‎11-28-2016

Re: clock out setting in mig 7 series and routing error

Hello @fpgalearner,


The option to enable additional clocks only appears if you're using the Vivado IP Integrator flow (block design).


As for the second 200MHz clock I would not route the MIG clock IOBUF and use it at another point.  Instead I would look at the Clocking Wizard IP and consider what other clocking sources are available in your design and generate the additional clock that way.  If it has to be a dedicated clock coming in from a CCIO pin then your options are limited since these are IP requirements.