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Observer startnexys3
Observer
3,525 Views
Registered: ‎04-02-2012

data read not correct use mig3.8 on atlys's ddr2

Hi,all.

I am a newer in mig.Recently, I try to generate the mcb to drive the digilent's atlys board's ddr2 memonry (MT47H64M16HR-25E). I use ise 13.2 and mig 3.8. Following the ug 388 and ug416, I successfully generated my own mcb, and i write simple vhdl code to test it(just write0H,1H,02H,03H,04H,05H...... into the ddr2, then read from it, write_cmd_bl=32, read_cmd_bl=32 too,the DATA_PORT_SIZE=32).

However, the read data has sth wrong, It is 0H,1H,02H,03H,04H,05H,06H,07H,AND THEN 21H 22H 23H 24H),I don't konw why.

 

here is the code, I read and write:

--------------------------------------------------------------
--write logic
--------------------------------------------------------------
wr:process(c3_p2_wr_clk)
variable cn:natural:=0;
variable wcn:natural:=0;
begin
if rising_edge(c3_p2_wr_clk) then
if(c3_p2_rst='1')then
waddr<=conv_std_logic_vector(0,30);
cn:=0;
wcn:=0;
elsif c3_p2_en='1' then
cn:=cn+1;
if cn=16 or wfull='1' then--
wlen<=conv_std_logic_vector(cn-1,6);
waddr<=conv_std_logic_vector(wcn,30);
wcn:=wcn+cn+1;-- change 32 to cn 7.7.10.35
cn:=0;
wcen<='1';
end if;
else
if cn>1 then--
wlen<=conv_std_logic_vector(cn-1,6);
waddr<=conv_std_logic_vector(wcn,30);
wcen<='1';
cn:=0;
end if;
end if;

if wcen/='0' then
wcen<='0';
end if;
end if;
end process;
wen<=c3_p2_en;
c3_p2_wr_full<=wfull;
c3_p2_wr_empty<=wempt;

--read logic
rd:process(c3_p3_rd_clk)
constant rdbatch:natural :=32;
variable cn:natural:=1;
variable rcn:natural :=0;
begin
if rising_edge(c3_p3_rd_clk) then
if(c3_p3_rst='1') then
raddr<=conv_std_logic_vector(0,30);
cn:=rdbatch;
rcn:=0;
elsif c3_p3_en='1' then
if ( cn>=rdbatch ) then-- or or rempt='1'
rdlen<=conv_std_logic_vector(rdbatch-1,6);
raddr<=conv_std_logic_vector(rcn,30);
rcn:=rcn+rdbatch;
cn:=0;
rcen<='1';
end if;
cn:=cn+1;
end if;

if rempt='0' then
ren<='1';
else--if rempt='1' then
ren<='0';
end if;

if rcen/='0' then
rcen<='0';
end if;
end if;
end process;

 

and followed my project,,,,

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3 Replies
Observer startnexys3
Observer
3,522 Views
Registered: ‎04-02-2012

Re: data read not correct use mig3.8 on atlys's ddr2

Here is my chipscope's screen shoot,the read data jump up and down......

csbus.png

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Observer startnexys3
Observer
3,513 Views
Registered: ‎04-02-2012

Re: data read not correct use mig3.8 on atlys's ddr2

I konw where i went wrong, I regard the byte address as word address, now it can work.

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Highlighted
Observer boy_fpga
Observer
3,257 Views
Registered: ‎10-01-2011

Re: data read not correct use mig3.8 on atlys's ddr2

can you explain it better? I'm trying to implement the code

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