We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!


init_calib_complete at low

Posts: 94
Registered: ‎12-05-2016

init_calib_complete at low

hi all,

i am posting this message to get a clarification for one reply in this thread. 




The issue with Mig core was that the reset pin was always high ( RTL miss )

Also the communication between DDR and pcie got established. The issue was that the inverted reset out of DDR has to be the reset input for the ddr. as soon as made this change in the RTL the DDR is up.

what is the meaning of this message? 

MIG is having one reset input "sys_rst" and a reset output "ddr3_reset_n". Do i need to map this output to input?

is it the meaning of this message? 

please do reply. I hope that it can solve all my problems related to MIG.

thanks in advance. 



Xilinx Employee
Posts: 3,313
Registered: ‎02-06-2013

Re: init_calib_complete at low



Sys_rst is input to the core and ddr3_reset_n is an output driven by the controller to the external DDR3 module and they shouldn't be looped back.


Sys_rst will have a polarity selection during the core generation and it should be driven by external hardware or internal logic based on the selected polarity.


Mig example design will have this generated correctly as per your selection and you can refer to it.



Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.