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866 Views
Registered: ‎03-28-2018

init_calib_complete is asserted only if DM pins is used

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Hello all,

 

I was trying to make a simple design to read and write from memory using MIG IP (user interface) on KC705. I followed this tutorial to customize the IP:

https://www.xilinx.com/support/documentation/boards_and_kits/kc705/2014_3/xtp196-kc705-mig-c-2014-3.pdf

 

The only difference to this tutorial is that I decided to not used DM and I un-checked the box to save I/O. Init_calib_complete was always low (The example design works fine on my KC705 board). Then after I decided to re-cutomize the MIG to use data mask and suddenly init_calib_complete and app_rdy are asserted after power on as expected. My app_wdf_rdy stays low, but this is may be for another post.

 

Here is my configurations:

Vivado Project Options:
   Target Device                   : xc7k325t-ffg900
   Speed Grade                     : -2
   HDL                             : vhdl
   Synthesis Tool                  : VIVADO

MIG Output Options:
   Module Name                     : mig_0
   No of Controllers               : 1
   Selected Compatible Device(s)   : --

FPGA Options:
   System Clock Type               : Differential
   Reference Clock Type            : Use System Clock
   Debug Port                      : OFF
   Internal Vref                   : disabled
   IO Power Reduction              : ON
   XADC instantiation in MIG       : Enabled

Extended FPGA Options:
   DCI for DQ,DQS/DQS#,DM          : enabled
   Internal Termination (HR Banks) : 50 Ohms
    
/*******************************************************/
/*                  Controller 0                       */
/*******************************************************/
Controller Options :
   Memory                        : DDR3_SDRAM
   Interface                     : NATIVE
   Design Clock Frequency        : 1250 ps (  0.00 MHz)
   Phy to Controller Clock Ratio : 4:1
   Input Clock Period            : 5000 ps
   CLKFBOUT_MULT (PLL)           : 8
   DIVCLK_DIVIDE (PLL)           : 1
   VCC_AUX IO                    : 2.0V
   Memory Type                   : SODIMMs
   Memory Part                   : MT8JTF12864HZ-1G6
   Equivalent Part(s)            : --
   Data Width                    : 64
   ECC                           : Disabled
   Data Mask                     : enabled
   ORDERING                      : Normal

AXI Parameters :
   Data Width                    : 512
   Arbitration Scheme            : RD_PRI_REG
   Narrow Burst Support          : 0
   ID Width                      : 4

Memory Options:
   Burst Length (MR0[1:0])          : 8 - Fixed
   Read Burst Type (MR0[3])         : Sequential
   CAS Latency (MR0[6:4])           : 11
   Output Drive Strength (MR1[5,1]) : RZQ/7
   Controller CS option             : Enable
   Rtt_NOM - ODT (MR1[9,6,2])       : RZQ/6
   Rtt_WR - Dynamic ODT (MR2[10:9]) : Dynamic ODT off
   Memory Address Mapping           : BANK_ROW_COLUMN


Bank Selections:

System_Clock: 
	SignalName: sys_clk_p/n
		PadLocation: AD12/AD11(CC_P/N)  Bank: 33

System_Control: 
	SignalName: sys_rst
		PadLocation: No connect  Bank: Select Bank
	SignalName: init_calib_complete
		PadLocation: No connect  Bank: Select Bank
	SignalName: tg_compare_error
		PadLocation: No connect  Bank: Select Bank

Does someone know what is happening here?

 

Thank you.

 

Regards,

Zaki

Regards,
Zaki
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1 Solution

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Moderator
Moderator
1,245 Views
Registered: ‎11-28-2016

Re: init_calib_complete is asserted only if DM pins is used

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Hello @mahmoud.sz.ragab,

 

My first thought is if the DM pins are disabled then they're left floating in the design would could inadvertently cause data to be 'masked' which would result in the incorrect data being written to the memory and then cause calibration stage to fail when the incorrect data is read back.

 

Since you're using a KC705 and won't be able to use those DM pins for any other purpose you might as well leave them enabled.

4 Replies
Moderator
Moderator
1,246 Views
Registered: ‎11-28-2016

Re: init_calib_complete is asserted only if DM pins is used

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Hello @mahmoud.sz.ragab,

 

My first thought is if the DM pins are disabled then they're left floating in the design would could inadvertently cause data to be 'masked' which would result in the incorrect data being written to the memory and then cause calibration stage to fail when the incorrect data is read back.

 

Since you're using a KC705 and won't be able to use those DM pins for any other purpose you might as well leave them enabled.

852 Views
Registered: ‎03-28-2018

Re: init_calib_complete is asserted only if DM pins is used

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Hi ryana,

 

Interesting thought.

So actually if I am using FPGA device connected to an external SDRAM (rather than a board with intergrated SO-DIMM module), I will have to ground the DM pins myself on the PCB if I decided to disable them during MIG customization, right?

So for a board with a so-dimm module it does not make sense to disable DM. I actually have falsely thought that when I disable DM it will be grounded (but then there is no I/O saving anyway)

 

Regards,

Zaki

 

 

Regards,
Zaki
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Moderator
Moderator
833 Views
Registered: ‎11-28-2016

Re: init_calib_complete is asserted only if DM pins is used

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Hello @mahmoud.sz.ragab,

 

Correct.  If you don't want to use the DM pins on your own board then they need to be grounded. Here is the recommendation from UG586 for this scenario:

dm-pin_ground.PNG

827 Views
Registered: ‎03-28-2018

Re: init_calib_complete is asserted only if DM pins is used

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Hey ryana,

Thank you really for spending time to answer what is clearly in the official docs.
Regards,
Zaki