01-02-2017 08:50 PM
i am using pcie and ddr in my project. first i interfaced pcie and verified the working by sending and receiving data. then i added MIG to my design then i found one error;
[Opt 31-304] Invalid connectivity on net sys_clk_n_IBUF between IBUF sys_clk_n_IBUF_inst and IBUFDS cmp2/u_mig_7series_0_mig/u_ddr3_clk_ibuf/diff_inpu
what may be the possible reasons for that?
01-03-2017 01:11 AM
No, that should not be the reason for this error.
This second IBUFDS_GTE2 is inside cmp3 instance, check this.
01-02-2017 09:44 PM - edited 01-02-2017 09:47 PM
Are you driving single ended or differential clock to sys_clk input of MIG IP?
It looks like you have selected "differential" for "system clock" while generating MIG IP but connecting single ended clock. Please reconfigure the MIG IP and select "single ended" for system clock.
Also the input buffer (IBUF or IBUFDS) will be present on the sys_clk port inside the core, so you need not instantiate any buffers at top level.
Are you driving the MIG IP and other user logic from same clock input?, if yes then please select "no buffer" for "system clock" during customization of MIG IP.
01-02-2017 10:33 PM
From the error it looks you are using single ended buffers on top of the differential buffer generated as part of the core and it is causing errors.
Make sure there is no cascading of buffers and you use the buffers generated with the core or use the no buffer option during core generation.
01-03-2017 12:21 AM
thankz for your response.
i am using the same sys_clk for for both MIG and pcie controller. i will change sys_clk option as no buffer. then what about the reference clock? i was selecting the option "use system clock".
01-03-2017 12:23 AM
You need not change reference clock option.
01-03-2017 12:31 AM
Instantiate IBUFDS in top level and connect IBUFDS output to MIG IP and PCIe IP.
01-03-2017 12:55 AM
hi, i did the same as follows,
IBUFGDS_inst : IBUFGDS
generic map (
-- DIFF_TERM => FALSE, -- Differential Termination
-- IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE)
IOSTANDARD => "DEFAULT")
port map (
O => clk_i, -- Clock buffer output
I => sys_clk_p, -- Diff_p clock buffer input (connect directly to top-level port)
IB => sys_clk_n-- Diff_n clock buffer input (connect directly to top-level port)
but it is showing the error,
[Synth 8-5535] port <sys_clk_p> has illegal connections. It is illegal to have a port connected to an input buffer and other components. The following are the port connections :
Port I of instance IBUFGDS_inst(IBUFGDS) in module <top_mod>
Port I of instance \cmp3/refclk_ibuf (IBUFDS_GTE2) in module top_mod.
01-03-2017 12:59 AM
The error says that you have connected port sys_clk_p to two input buffers IBUFGDS_inst and refclk_ibuf hence the error. You can connect it to only one buffer. Check where is this refclk_ibuf instantiated and remove it if it is not needed.