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invalid connectivity on net sys_clk

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Adventurer
Posts: 83
Registered: ‎12-05-2016
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invalid connectivity on net sys_clk

hi,

i am using pcie and ddr in my project. first i interfaced pcie and verified the working by sending and receiving data. then i added MIG to my design then i found one error;

[Opt 31-304] Invalid connectivity on net sys_clk_n_IBUF between IBUF sys_clk_n_IBUF_inst and IBUFDS cmp2/u_mig_7series_0_mig/u_ddr3_clk_ibuf/diff_input_clk.u_ibufg_sys_clk. This is a dedicated connection.

what may be the possible reasons for that? 

 regards,

Reshma


Accepted Solutions
Posts: 5,573
Kudos: 753
Solutions: 999
Registered: ‎09-20-2012

Re: invalid connectivity on net sys_clk

No, that should not be the reason for this error.

 

This second IBUFDS_GTE2 is inside cmp3 instance, check this.

Thanks,
Deepika.
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Posts: 5,573
Kudos: 753
Solutions: 999
Registered: ‎09-20-2012

Re: invalid connectivity on net sys_clk

[ Edited ]

Hi @reshmaakhil

 

Are you driving single ended or differential clock to sys_clk input of MIG IP?

 

It looks like you have selected "differential" for "system clock" while generating MIG IP but connecting single ended clock. Please reconfigure the MIG IP and select "single ended" for system clock.

 

Also the input buffer (IBUF or IBUFDS) will be present on the sys_clk port  inside the core, so you need not instantiate any buffers at top level.

 

Are you driving the MIG IP and other user logic from same clock input?, if yes then please select "no buffer" for "system clock" during customization of MIG IP.

Thanks,
Deepika.
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Moderator
Posts: 3,274
Registered: ‎02-06-2013

Re: invalid connectivity on net sys_clk

Hi

 

From the error it looks you are using single ended buffers on top of the differential buffer generated as part of the core and it is causing errors.

 

Make sure there is no cascading of buffers and you use the buffers generated with the core or use the no buffer option during core generation.

Regards,

Satish

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Adventurer
Posts: 83
Registered: ‎12-05-2016

Re: invalid connectivity on net sys_clk

hi,

thankz for your response.

i am using the same sys_clk for for both MIG and pcie controller. i will change sys_clk option as no buffer. then what about the reference clock? i  was selecting the option "use system clock".

regards,

Reshma

Posts: 5,573
Kudos: 753
Solutions: 999
Registered: ‎09-20-2012

Re: invalid connectivity on net sys_clk

Hi @reshmaakhil

 

You need not change reference clock option.

Thanks,
Deepika.
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Adventurer
Posts: 83
Registered: ‎12-05-2016

Re: invalid connectivity on net sys_clk

hi, now the sys_clk changed to a single ended, but my top module input is differential. what can i do for that?

Posts: 5,573
Kudos: 753
Solutions: 999
Registered: ‎09-20-2012

Re: invalid connectivity on net sys_clk

Hi @reshmaakhil

 

Instantiate IBUFDS in top level and connect IBUFDS output to MIG IP and PCIe IP.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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Adventurer
Posts: 83
Registered: ‎12-05-2016

Re: invalid connectivity on net sys_clk

hi, i did the same as follows,

IBUFGDS_inst : IBUFGDS
generic map (
-- DIFF_TERM => FALSE, -- Differential Termination
-- IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE)
IOSTANDARD => "DEFAULT")
port map (
O => clk_i, -- Clock buffer output
I => sys_clk_p, -- Diff_p clock buffer input (connect directly to top-level port)
IB => sys_clk_n-- Diff_n clock buffer input (connect directly to top-level port)
);

but it is showing the error,

[Synth 8-5535] port <sys_clk_p> has illegal connections. It is illegal to have a port connected to an input buffer and other components. The following are the port connections :
Input Buffer:
Port I of instance IBUFGDS_inst(IBUFGDS) in module <top_mod>
Other Components:
Port I of instance \cmp3/refclk_ibuf (IBUFDS_GTE2) in module top_mod.

regards,

Reshma

 

 

Posts: 5,573
Kudos: 753
Solutions: 999
Registered: ‎09-20-2012

Re: invalid connectivity on net sys_clk

Hi @reshmaakhil

 

The error says that you have connected port sys_clk_p to two input buffers IBUFGDS_inst and refclk_ibuf hence the error. You can connect it to only one buffer. Check where is this refclk_ibuf instantiated and remove it if it is not needed.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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Adventurer
Posts: 83
Registered: ‎12-05-2016

Re: invalid connectivity on net sys_clk

in the mig ip i selected the option "use system clock" for reference clock. does that cause problem?