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Visitor meisam_b
Visitor
893 Views
Registered: ‎04-28-2018

memory controller simulation

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I generated a memory interface for a Spartan 6 FPGA and I'm going to use it separately in my design.

At first, I want to simulate it alone. For this purpose I did these actions:

1- Create new project in ISE 14.7 

2- Add rtl files from folder "E:\ISE_DSP_Example\MIG\MIG\ipcore_dir\MIG\user_design\rtl" to new design

3- Synthesis it

4- write test bench:

-- hold reset state for 100 ns.
wait for 100 ns;

wait for c3_p0_cmd_clk_period*10;

c3_sys_rst_i <='0';
c3_p0_cmd_en <='0';
c3_p0_cmd_instr <="000";
c3_p0_cmd_bl <= "000111";
c3_p0_cmd_byte_addr <= "00" & X"05AD3FD";

wait for 10 ns;
c3_p0_cmd_en <='1';
wait for 10 ns;
c3_p0_cmd_en <='0';

c3_p0_wr_en <='0';
c3_p0_wr_data <= X"00000000";
wait for 50 ns;
c3_p0_wr_en <='1';
c3_p0_wr_data <= X"C0C0C0C0";
wait for 10 ns;
c3_p0_wr_data <= X"C1C1C1C1";
wait for 10 ns;
c3_p0_wr_data <= X"C2C2C2C2";
wait for 10 ns;
c3_p0_wr_data <= X"C3C3C3C3";
wait for 10 ns;
c3_p0_wr_data <= X"C4C4C4C4";
wait for 10 ns;
c3_p0_wr_data <= X"C5C5C5C5";
wait for 10 ns;
c3_p0_wr_data <= X"C6C6C6C6";
wait for 10 ns;
c3_p0_wr_data <= X"C7C7C7C7";
wait for 10 ns;
c3_p0_wr_en <='0';

5- Simulation results exist in attachments (sim1.jpg, sim2.jpg, sim3.jpg)

6- Why memory interface signals of controller have no change(sim2.jpg)?

sim1.jpg

sim1.jpg

sim2.jpg

sim2.jpg

sim3.jpg

sim3.jpg

If you don't find the problem of my design please guide me how I can use memory controller in my own design step by step please. I'm a little stupid.

If need much data please tell me.

 

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Moderator
Moderator
1,095 Views
Registered: ‎02-11-2014

Re: memory controller simulation

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Hello @meisam_b,

 

The provided test bench is just an example. You can modify it to do whatever you like. That is as much guidance as we can provide.

 

Thanks,

Cory

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5 Replies
Moderator
Moderator
826 Views
Registered: ‎02-11-2014

Re: memory controller simulation

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Hello @meisam_b,

 

We provide a sample test bench in /mig/example_design/sim/functional. Please try out this and then use this logic to create your own test bench.

 

Thanks,

Cory

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Visitor meisam_b
Visitor
808 Views
Registered: ‎04-28-2018

Re: memory controller simulation

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Hello Cory

I will try it and present the results.

Thanks

meisan

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Visitor meisam_b
Visitor
803 Views
Registered: ‎04-28-2018

Re: memory controller simulation

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I have a question.

Does it need I read that complex design for using MCB in my design? or I can use it simpler. I think i don't need read all codes.

Is there a simple way to use MCB? if YES please tell me.

 

Thanks

Meisam

 

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Visitor meisam_b
Visitor
787 Views
Registered: ‎04-28-2018

Re: memory controller simulation

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Is there any body help me please?

I need a sample test bench for memory controller block of spartan 6 user_design.

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Highlighted
Moderator
Moderator
1,096 Views
Registered: ‎02-11-2014

Re: memory controller simulation

Jump to solution

Hello @meisam_b,

 

The provided test bench is just an example. You can modify it to do whatever you like. That is as much guidance as we can provide.

 

Thanks,

Cory

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Don’t forget to reply, kudo, and accept as solution.
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