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Visitor uta
Visitor
24,159 Views
Registered: ‎07-14-2011

possible to swap pin at DDR3 memory side?

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Hi,

 

Wish to seek advice for following concerns:

 

a) Possible to swap pin at DDR3 chip side for entire byte lane?

e.g. entire D[0:7] swap with entire D[8:15]

 

b) It's understood that byte-to-byte swapping is usually allowable at FPGA controller (which consists of many banks). But does this rule applicable for other SoC in general?

1 Solution

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Teacher eteam00
Teacher
31,623 Views
Registered: ‎07-21-2009

RESTATED: DDR2 and DDR3 rules for circuit board signal swapping

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Entire byte lanes may be swapped, signal for signal (DQ for DQ, DM for DM, DQS pair for DQS pair)

 

Above statements is applicable for DDR3 chip itself, right?

 

Yes, for either DDR3 or DDR2.

 

For a x16 DRAM, a byte lane swap is defined as making ALL of the substitutions below:

 

      Lower byte lane <=> Upper byte lane

              DQ07:00 <=> DQ15:08

                  LDM <=> UDM

diff pair LDQS, LDQS* <=> diff pair UDQS, UDQS*

 

In addition, the following bit swaps are allowable for x4, x8, or x16 DDR2 or DDR3 devices:

 

                    Any of these bits: DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7

may be swapped with any of these bits: DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7

 

                    Any of these bits: DQ08, DQ09, DQ10, DQ11, DQ12, DQ13, DQ14, DQ15

may be swapped with any of these bits: DQ08, DQ09, DQ10, DQ11, DQ12, DQ13, DQ14, DQ15

 

A memory module (DIMM or SO-DIMM) typically has 8 byte lanes.  Any of the 8 byte lanes may be swapped with one of the other byte lanes.

 

This has all been written and posted before, but sometimes it helps to repeat the same information written in a number of different ways -- especially when language translation may be imprecise.

 

-- Bob Elkind

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16 Replies
Scholar drjohnsmith
Scholar
24,156 Views
Registered: ‎07-09-2009

Re: possible to swap pin at DDR3 memory side?

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Basicaly no is a good answer.

 

the data bus is used to comunicate commands to the ddr3 chips !

     so if you twiddle the data bus around, you twiddle the commands, not a good idea.

 

you might be able to swap pins on the fpga, depending which fpga you have,

    so say D8 comes out of another pin, 

         but that has a set of second problems meeting timing .

 

DDR3 is a **** challenge to get working timmings if your pushing the bounds.

      as soon as yo go away form what the MIG tools generate your intio big heart ach.

 

 

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Teacher eteam00
Teacher
24,150 Views
Registered: ‎07-21-2009

UPDATED: DDR2 and DDR3 rules for circuit board signal swapping

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This post addresses (pun intended) the rules for swapping signals on the circuit board between the FPGA and the DRAM device(s), typically for optimising circuit board routing.  Such signal swapping is performed on the circuit board (and is represented in the circuit board schematics), and does not affect the FPGA design, including device pin assignments.

 

Here are the rules for swapping (assuming a single DRAM device):

 

For a 4-bit or 8-bit DRAM, you can swap DQ signals on the board without a care.  All of the DQ pins are interchangeable.  If FPGA DQ5 is connected to DRAM DQ0, and FPGA DQ0 is connected to DRAM DQ5, neither the DRAM nor the FPGA (or MCB) will care.

 

For a 16-bit DRAM, the rules are a bit tighter-- just a little bit tighter.  Here they are:

  • DQ0 through DQ7 are entirely equivalent, and can be interchanged without fear.
  • DQ8 through DQ15 are entirely equivalent, and can be interchanged without fear.
  • You must not interchange any of the DQ0-7 signals or pins with any of the DQ8-15 pins or signals.

A 16-bit DRAM has two byte lanes.  Each byte lane consists of a Strobe (DQS pair), Mask (DM), and Data (DQ pins).  There are logic (control) and timing relationships which bond the 11 byte lane signals together as a group, and you must not intermingle the signals from multiple byte lanes.  For a 16-bit DRAM, the two byte lanes are labeled U (for Upper) and L (for Lower).

 

If you are interested, you can interchange an entire byte lane with another entire byte lane.  This might help you, or maybe not.  You can implement this 1-for-1 byte lane swap concurrently with swapping DQ pins within a single byte lane, it won't make a difference.

 

Rules which apply for multi-DRAM designs (e.g. DIMMs and SO-DIMMs):

 

As in the case of x16 DRAMs described above

  • DQ (data) signal swapping within each byte lane is acceptable
  • Entire byte lanes may be swapped, signal for signal (DQ for DQ, DM for DM, DQS for DQS)
  • Individual DQ (data bit) signals may not be swapped between byte lanes

 

An added note:

Q.  What swapping is allowed for DRAM Address (Ax) or Bank Address (BAx) signals?

A.  None. The address and bank address signals are used to convey opcodes loaded into the mode registers internal to the DRAM.  Swapping the address and bank address signals will result in non-functional memory.  Also, some address bits are used to convey both row and column address, and some are not.  The address and bank address bits are not swappable.

I hope this helps.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
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4. Do not post a new topic or question on someone else's thread, start a new thread!
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Scholar drjohnsmith
Scholar
24,141 Views
Registered: ‎07-09-2009

Re: DDR2 and DDR3 rules for circuit board signal swapping

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Well done,

 

how about makign this a sticky or app note

 

 

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Xilinx Employee
Xilinx Employee
24,141 Views
Registered: ‎10-23-2007

Re: DDR2 and DDR3 rules for circuit board signal swapping

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There is one more obscure potential issue with DDR3 data bit swapping even if the controller doesn't use the MPR noted in eteam00's post.  That is with write leveling.  Controllers with more than a single component and even some with only one (Virtex-6 for MIG, for example), will do write leveling.  The active return DQ ("prime DQ") for the write leveling can be either a single bit or the entire byte lane.  It is up to the memory vendor.  If the entire byte lane is active, then there is no swap issue.  But if only one bit is used, you'd need to be careful about swapping it.

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Teacher eteam00
Teacher
24,137 Views
Registered: ‎07-21-2009

Defending JEDEC DDR3 standard: write leveling

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@jschmitz,

 

Controllers with more than a single component and even some with only one (Virtex-6 for MIG, for example), will do write leveling.  The active return DQ ("prime DQ") for the write leveling can be either a single bit or the entire byte lane.  It is up to the memory vendor.  If the entire byte lane is active, then there is no swap issue.  But if only one bit is used, you'd need to be careful about swapping it.

 

NOTE:  this post concerns only DDR3 designs.

 

Executive Summary:

  • The problem described in jschmitz' post is evidence of a non-compliant memory controller design.
  • A JEDEC-compliant DDR3 memory controller has no such bit-swap sensitivity with write leveling, or with any other transaction or function.
  • Xilinx Virtex-6, Spartan-6, and Gen-7 memory controller IPs do NOT have the problem described by jspaldings.

 

Long technical explanation of DDR3 design and Jedec standard as it relates to this question:

 

  • The JEDEC DDR3 standard does not specify which DQ (in a byte lane) is to be the 'prime DQ'.  By requiring all non-prime DQs to be '0', the JEDEC standard ensures detection of the 'prime DQ' by the controller.
  • DRAM device manufacturers are not obligated to establish or maintain a consistent and unchanging 'prime DQ' bit selection, or to match Micron's current design selection.
  • DIMM/SO-DIMM manufacturers are allowed to (and will) swap DQ signals within byte lanes, rendering DRAM manufacturer's prime DQ identification moot.  Even worse, two-rank modules may have un-matched DQ swapping for each of the two ranks. [note:  from JEDEC 21C -- DQ-to-I/O wiring is shown as recommended but may be changed.]
  • In order to maintain compatibility with various DRAMs and modules, memory controllers are obligated to detect any DQ bit which might be 'prime'.

This is rather an important issue.

 

The point of an industry standard (JEDEC JESD79-3E, for example) is to allow and ensure industry compatibility.  The JEDEC DDR3 standards (devices, modules) do not specify a 'prime DQ'.  JEDEC considers a specification of the 'prime DQ' unnecessary for industry compatibility.

 

By the way, there are some memory controllers (Freescale 8536 comes to mind) which do not 'do the right thing' with respect to this very point.  As an example, such a shortcoming is considered an 'erratum', rather than a 'feature', by Freescale (erratum, page 24).

 

If we still have your attention, would you happen to know which of the current Xilinx [soft | mixed | hard] memory controllers support either write leveling or read leveling for DDR3 ?

 

Thank you kindly,

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Xilinx Employee
Xilinx Employee
24,117 Views
Registered: ‎10-23-2007

Re: DDR3 rules for circuit board signal swapping

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The Virtex-6 and 7 Series DDR3 memory controllers generated by MIG perform write and read leveling.  The Spartan-6 hard MCB does not.  Both the Virtex-6 and 7 Series controllers OR the bits for the write leveling process so it does not matter which bit returns the data (the others are guaranteed to be zero).

 

Sorry to alarm you, I was speaking of DDR3 controllers in general, not necessarily specific FPGA designs.

Teacher eteam00
Teacher
24,089 Views
Registered: ‎07-21-2009

Re: UPDATED: DDR2 and DDR3 rules for circuit board signal swapping

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In my original post #3 in this thread, I included a description of a DDR3 read-leveling (MPR read) mode which would preclude bit-swapping within a byte lane.

 

My understanding of this mode was incorrect.  There is no obstacle to bit-swapping (within a byte lane) for Jedec-compliant DDR3 memory controllers, or in the Jedec DDR3 standard.

 

I have updated (corrected) post #3, with the DDR3 read-leveling issue deleted.

 

Apologies for the confusion.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor uta
Visitor
24,085 Views
Registered: ‎07-14-2011

Re: UPDATED: DDR2 and DDR3 rules for circuit board signal swapping

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based on above posts, sorry but i wish to clarify again:

 

  • Entire byte lanes may be swapped, signal for signal (DQ for DQ, DQM for DQM, DQS for DQS)

Above statements is applicable for DDR3 chip itself, right?

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Teacher eteam00
Teacher
31,624 Views
Registered: ‎07-21-2009

RESTATED: DDR2 and DDR3 rules for circuit board signal swapping

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Entire byte lanes may be swapped, signal for signal (DQ for DQ, DM for DM, DQS pair for DQS pair)

 

Above statements is applicable for DDR3 chip itself, right?

 

Yes, for either DDR3 or DDR2.

 

For a x16 DRAM, a byte lane swap is defined as making ALL of the substitutions below:

 

      Lower byte lane <=> Upper byte lane

              DQ07:00 <=> DQ15:08

                  LDM <=> UDM

diff pair LDQS, LDQS* <=> diff pair UDQS, UDQS*

 

In addition, the following bit swaps are allowable for x4, x8, or x16 DDR2 or DDR3 devices:

 

                    Any of these bits: DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7

may be swapped with any of these bits: DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7

 

                    Any of these bits: DQ08, DQ09, DQ10, DQ11, DQ12, DQ13, DQ14, DQ15

may be swapped with any of these bits: DQ08, DQ09, DQ10, DQ11, DQ12, DQ13, DQ14, DQ15

 

A memory module (DIMM or SO-DIMM) typically has 8 byte lanes.  Any of the 8 byte lanes may be swapped with one of the other byte lanes.

 

This has all been written and posted before, but sometimes it helps to repeat the same information written in a number of different ways -- especially when language translation may be imprecise.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Visitor uta
Visitor
7,864 Views
Registered: ‎07-14-2011

Re: UPDATED: DDR2 and DDR3 rules for circuit board signal swapping

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Thank you very much for your useful information. Appreciate it.

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Visitor fls50
Visitor
7,273 Views
Registered: ‎12-18-2012

Re: UPDATED: DDR2 and DDR3 rules for circuit board signal swapping

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The byte lane discussion is very helpful.  what about the DDR3 clock, address and control signals.  Are there any limitaions on swapping or placing those?

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Visitor bunrector
Visitor
5,537 Views
Registered: ‎05-19-2008

Re: possible to swap pin at DDR3 memory side?

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So I know that it has already been said that all memory controllers are not created equal to the standard, but how pray tell does FreeScale place this in there I.MX6 design guide regarding bit swapping of a byte lane:

 

"The rules are as follows:

 

  Hardware write leveling – lowest order bit within byte lane must remain on lowest order bit of lane by JEDEC compliance (see the “Write Leveling” section in JESD79-3E)

   — D0, D8, D16, D24, D32, D40, D48, and D56 are fixed

   — Other data lines free to swap within byte lane"  -IMX6DQ6SDLHDG Rev 1  06/2013  (page 3-10 section 3.5.1)

 

(http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf)

 

I read the section in JESD79-3E about write leveling, and it said nothing about keeping D0, D8, D16, D24, D32, D40, D48, and D56 fixed. The only thing I recall it saying is that you should strobe one DQ or all DQs and leave the unused DQs low.  Why would Freescale put this in their document? Does this mean that their controller will only work with RAM that uses the lowest ordered bit in a byte group as the Prime bit?

 

They reference the JEDEC standard, but the I didn't see their claim in the standard? Did I miss it?

 

Thanks,

 

Bun

 

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Contributor
Contributor
3,814 Views
Registered: ‎04-18-2015

Re: possible to swap pin at DDR3 memory side?

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Hi all,

We are doing a PCB design that involves ZYNQ XC7Z045-1FFG900I and 2 DDR3 memories(MT41J128M16JT-187EITK) IN X16 configuration with total 32 bit organization. Both the DDR3 is connected to PS side of the ZYNQ that having dedicated pins. our pcb is very complex because of that we are not able to route the lines directly to pins of ddr3.so any pin swapping is possible in ZYNQ PS side? if not whether DDR3 side pin swapping is allowed?

regards

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Moderator
Moderator
3,801 Views
Registered: ‎11-28-2016

Re: possible to swap pin at DDR3 memory side?

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Hello @harikrishnani,

 

In the future it's always best to create a new thread for your question.  Otherwise it will be buried in a much older thread and will not have visibility with the other users in the forum.

 

The Zynq-7000 PS interface pin swapping guidelines are mentioned in UG933 on page 66:Zynq-7000_swapping.PNG

Since you have a DDR3 design then you are allowed to swap all the bits within the byte, but they still must remain within that byte.  You also need to keep the same DQS with that byte.

 

Here's a link to the latest version of UG933:

http://www.xilinx.com/support/documentation/user_guides/ug933-Zynq-7000-PCB.pdf

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Visitor nidhi.jani
Visitor
3,373 Views
Registered: ‎04-03-2018

Re: RESTATED: DDR2 and DDR3 rules for circuit board signal swapping

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Hello,

 

Can you please tell me that if i want to swap x64 DDR, how i can swap that?

What are the Swapping rules for x64 DDR ?

i m using MT4HTF3264AH-256MB.

please guide me regarding this as soon as possible.

 

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Moderator
Moderator
3,368 Views
Registered: ‎02-11-2014

Re: RESTATED: DDR2 and DDR3 rules for circuit board signal swapping

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Hello @nidhi.jani,

 

Please post your question as a new topic we we can get is answered for you.

 

Thanks,

Cory

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