05-11-2019 11:20 AM - edited 05-11-2019 11:22 AM
Hi, I'm Jose
I have an kc705 evaluation board. I am writing to and reading from the memory. I am accessing in the next way
1- WRITING: Access bank 0-row 0 and write to fill up all the columns (2^10 columns) in that row. Next, access bank 1-row 0 and write to fill up all the columns in that row. Next, access bank 2-row 0 and write to fill up all the columns in that row. ..and so on....... Next, access bank 7-row 0 and write to fill up all the columns in that row. after that, pass to the next row, i.e, bank 0-row 1 and so on till bank 7-row 1. And so on, the row is incremented after using the 8 banks.
NOTE: as I am using a burst of 8, in each row of a bank I have a max of 128 accesses (128*8 = 1024 colums). and I write in every access a number corresponding to the number of the access. I mean
bank 0, row0
access 1 2 3 4 5 6..........128
data to be written 1 2 3 4 5 6...........128
in every row the same data is written: data from 1 to 128
2-In order to see if all the data were written correctly I read the same addresses in which I previously Wrote. but I have a problem, I'd wait that the data should appear sequencially from 1 to 128 in the app_rd_data bus, but It is no the case. In the image I attached I show the data I am reading from the memory; to the left of the red line are shown the data of the bank0 row0 and those are read correctly , I mean they appeared sequentially from 1 to 128 as expected. But when reading the data in bank1 row0 (to the right of the red line) the data are not read correctly because appear 1, 2 ,3, 4, 5,6, 117, 118, 119,11,12 (not sequentially as they have been written). the behavior repeats over other addresses, I put this as an example
anyone know why is this behavior? I reviewed the data that is been sending with the write command and it is fine. The addressing, the app_en and the read command that is been sending is fine too. am I loosing something about the read proccess?
thanks for your help
05-13-2019 02:47 AM
Are the address mapping= ROW_BANK_COLUMN at user interface? Is the read/write column address 0, 8h, 10h, ...etc?
05-13-2019 07:44 AM - edited 05-13-2019 07:45 AM
1- I generated the core with the option BANK_ROW_COLUMN not the one you are saying. How can it influence the behavior? I have understood that you choose one or other if you just want to increment efficiency.
2-yes, I am incrementing the column value with steps of 8, for writing and reading. I mean 0 8h, 10h ...
05-13-2019 04:50 PM
How do you design dram controller ? By MIG ?
If MIG, how do you define DRAM parameters ? Are they correct ?
It seems wrong latency issue.
Would you make sure the followings at least ?
- Read Latency
- Write Latency
- Additive Latency
05-13-2019 11:09 PM
Please take scopshot of the write operation including all the app_ signals at the uesr interface.
05-15-2019 12:40 PM
Hi guys, thank you for your help.
I could find the problem. the problem was that the app_en signal was working fine but the app_wdf_wren and app_wdf_end signals were not being asserted in some cases. So , that triggered that strange behavior.