11-09-2017 09:04 AM
we are designing a custom board with XCKU115-2FLVB1760I kintex ultrascale fpga, decided to add memory qdr2+ from cypress.so when we did the mig (memory interface generator) it is clear that x72 datawidth wont spport.is it true?so qdr2+ pinplanning in mig automatically done in 44,45,46 banks.
is there anymethod to change pinlocking to diffrent banks?
if x36 interface is maximum,then 2 qdr2+ we may have to add.second qdr2+ pinplanning done at 50,51,52,is it correct?
11-10-2017 08:30 AM - edited 11-12-2017 03:19 PM
The Byte Planner behaves as it should per PG150 "Pin and Bank Rules for QDRII+". I would also recommend looking in the "Feature Summary" section for native QDRII+ support. https://www.xilinx.com/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf
If you need more density you will need to make a custom CSV as shown in https://www.xilinx.com/support/answers/63462.html
We also have Board Guidelines for QDRII+ in UG583. Make sure to look in the "PCB Guidelines for Memory Interfaces" as well as the "PCB Guidelines for QDR II+ SRAM".
If you have any questions about QDRII+ pin planning please let me know.