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qdr2+ memory in xcku115 board

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Participant
Posts: 22
Registered: ‎04-18-2015

qdr2+ memory in xcku115 board

hi all,

we are designing a custom board with XCKU115-2FLVB1760I  kintex ultrascale fpga, decided to add memory qdr2+ from cypress.so when we did the mig (memory interface generator) it is clear that x72 datawidth wont spport.is it true?so qdr2+ pinplanning in mig automatically done in 44,45,46 banks.

is there anymethod to change pinlocking to diffrent banks?

if x36 interface is maximum,then 2 qdr2+ we may have to add.second qdr2+ pinplanning done at 50,51,52,is it correct?

Xilinx Employee
Posts: 48
Registered: ‎02-11-2014

Re: qdr2+ memory in xcku115 board

[ Edited ]

Hey @harikrishnani,

 

The Byte Planner behaves as it should per PG150 "Pin and Bank Rules for QDRII+". I would also recommend looking in the "Feature Summary" section for native QDRII+ support. https://www.xilinx.com/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf

 

If you need more density you will need to make a custom CSV as shown in https://www.xilinx.com/support/answers/63462.html

 

We also have Board Guidelines for QDRII+ in UG583. Make sure to look in the "PCB Guidelines for Memory Interfaces" as well as the "PCB Guidelines for QDR II+ SRAM".

https://www.xilinx.com/support/documentation/user_guides/ug583-ultrascale-pcb-design.pdf

 

If you have any questions about QDRII+ pin planning please let me know.

 

Thanks,

Cory

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