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Registered: ‎01-25-2019

what is the relationship between liner address used in programming languge such as C and SDRAM rank, bank group, bank, row, and column addresses

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Hi, I was trying to write DDRC ECC test code using C.

I followed ECC Poisoning instruction from the ug1085 manual page chapter 17.

it seems very difficult to understand the relationship between liner address I am using in c code to Rank, Bank group, Bank, Row, Colum address.

All I wanted to do is just write the specific memory address say 0x00200800U to DDRC.ECCPOISONADDR {0, 1} registers, and access that memory from c code such that ECC error will be introduced on that transaction.

please point me the to the right document or provide me with a mapping table to do just that.

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Registered: ‎11-28-2016

Re: what is the relationship between liner address used in programming languge such as C and SDRAM rank, bank group, bank, row, and column addresses

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Hello @sami.mahamoed ,

The first part of this question depends on the "Memory Address Map" option selected in the Zynq PS DDR Configuration GUI.  The next part comes from the actual memory device installed on the board since that will determine your address space.  From there you have a bit of AXI address to physical memory address translation.  For a simple case lets assume a ROW_BANK_COL with an 8Gbit x16 memory device.

From the memory device data sheet you'll see:
16 Row bits
10 Column bits
3 Bank bits

By default BG0 is always going to be your least significant bit in the useable address space, so the physical DDR memory mapping looks like:
Row[15:0]_BA[1:0]_Column[9:3]_BG[0]_Column[2:0]

Column[2:0] are mapped to the lower part of the address since these are always ignored with a Burst Length = 8 controller.

Next you'll have the physical DDR4 to logical Byte AXI address mapping.  If you have a 64-bit DDR4 interface then pad 3-bits of 0, and if you have a 32-bit DDR4 interface then pad 2-bits of 0 to the end.

Wrapping it all together if you have a 64-bit memory interface made of 8Gbit x16 components you'll have AXI Address 31 equivaelent to Row 15 and BG0 is mapped to AXI Address 6.  The AXI[5:0] bits are all mapped to 0; 3-bits for the lower Column addressing which is always 0 and 3-bits of 0 for the AXI Byte to DRAM burst size alignment.

Thanks,
Ryan.

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Moderator
Moderator
102 Views
Registered: ‎11-28-2016

Re: what is the relationship between liner address used in programming languge such as C and SDRAM rank, bank group, bank, row, and column addresses

Jump to solution

Hello @sami.mahamoed ,

The first part of this question depends on the "Memory Address Map" option selected in the Zynq PS DDR Configuration GUI.  The next part comes from the actual memory device installed on the board since that will determine your address space.  From there you have a bit of AXI address to physical memory address translation.  For a simple case lets assume a ROW_BANK_COL with an 8Gbit x16 memory device.

From the memory device data sheet you'll see:
16 Row bits
10 Column bits
3 Bank bits

By default BG0 is always going to be your least significant bit in the useable address space, so the physical DDR memory mapping looks like:
Row[15:0]_BA[1:0]_Column[9:3]_BG[0]_Column[2:0]

Column[2:0] are mapped to the lower part of the address since these are always ignored with a Burst Length = 8 controller.

Next you'll have the physical DDR4 to logical Byte AXI address mapping.  If you have a 64-bit DDR4 interface then pad 3-bits of 0, and if you have a 32-bit DDR4 interface then pad 2-bits of 0 to the end.

Wrapping it all together if you have a 64-bit memory interface made of 8Gbit x16 components you'll have AXI Address 31 equivaelent to Row 15 and BG0 is mapped to AXI Address 6.  The AXI[5:0] bits are all mapped to 0; 3-bits for the lower Column addressing which is always 0 and 3-bits of 0 for the AXI Byte to DRAM burst size alignment.

Thanks,
Ryan.

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