05-07-2018 10:57 AM
Why when we try to instantiate a MIG with the IP integrator on VIVADO the option AXI interface is automatically enabled whereas when we instantiate a MIG using the IP catalog the option AXI interface is automatically disabled?
05-07-2018 11:05 AM
Because of the context. In the IP Integrator (block diagrams), everything connects with AXI. The IP Catalog is more general purpose, and typically used for creating RTL blocks to drop into RTL designs. AXI can't be assumed in this case.
05-07-2018 11:13 AM
In IP integrator you can only use the AXI Interface (its ALWAYS enabled and ONLY enabled) for DDR2/DDR3. You cannot use QDRII+, QDR-IV, LPDDR2 and RLDRAM in IP Integrator. In IP Catalog, you can choose not to use the AXI Interface for DDR2/DDR3. QDRII+, QDR-IV, RPLDRAM and LPDDR2 will have the AXI Interface option greyed out by default as it is not usable. I am assuming you have something other than DDR2/DDR3 selected and that is why the AXI Interface option is greyed out and not select-able, but its difficult to see in your screenshot.
05-07-2018 01:47 PM
I am using the VC707 board and the IP catalog doesn't offer the option AXI interface.
My goal is to use he IP generator as mentionned in this tutorial https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-getting-started-with-microblaze-servers/start to establish a ethernet connection between the FPGA and a PC.
Is there a testbench example that tests the MIG with the AXI interface?
05-07-2018 02:28 PM
Those are steps for using an ARTY board and not for a VC707.
IP Catalog does allow you to use the AXI Interface for DDR2/DDR3 Only with Verilog language only per UG586:
If you have the AXI Interface enabled and you build the IP Example Design, you will be delivered a sample AXI TG and a sample Test Bench for AXI.
05-08-2018 07:08 AM
Yes you can do a similar flow since it looks like they are just setting up a Block Diagram in their setup guide.