10-10-2018 08:36 AM
I'm trying to implement switchable 10G/1G transceiver. Something like this: https://www.xilinx.com/support/documentation/application_notes/xapp1243-1g-10g-switching.pdf , but for Zynq UltraScale+ ZCU102 Evaluation Board, vivado 2017.4, PCS core is desirable but not necessary.
The plan was:
1. Make 10g and 1g ip cores into wizard.
2. Compare parameters and ports.
3. Add absent ports into 10g core.
4. Connect 10g core with user logic. Use specific 10g/1g ports depends on mode.
5. Change parameters through DRP depends on mode.
I have difficulties with making ip core in wizard. Some settings there are blocked. For example, port gtwiz_userclk_tx_reset_in cannot be added if pll type is qpll (10g core), but it is used in 1g core. If i select cpll in 10g core, it is not possible to select needed "Actual Reference clock" ( minimum clock in select list is 206.25 MHz, but actual is 156.25 MHz).
Is there any workaround? Or maybe better way to make switchable 10G/1G transceiver?
10-10-2018 09:17 AM
I will be interesetd in implementing 1G/10G switching subsystem as well in the near future.
As far as I know in Vivado 2018.2 there is a dedicated IP (https://www.xilinx.com/products/intellectual-property/1g-10g-25ge.html#documentation). It still lacks much documentatiojn and examples.
Maybe someone from Xilinx could help.
10-10-2018 09:51 AM
Thanks for the advice. I have tried to use this core. It is not suitable, because requires additional license for some 1g cells. Also it takes too many resources, about 30000 luts and registers for quad.
10-17-2018 10:05 AM
I've tried to use the 1G/10G/25G Switching Ethernet Subsystem ipcore again. It doesn't require additional license without Auto Negotiation (Clause 73).
Also it takes two times less resources without AN, about 16000 luts and 20000 registers for quad.
There are some errors into example design:
1. Many ports inside generated example modules were without nettype. (It is a problem if you use `default_nettype none).
2. Some signals weren't declared, (gtwiz_buffbypass_rx_error_out, gtwiz_buffbypass_tx_error_out, rx_protocol_error, gmii_rx_sent_overflow, gmii_rx_total_bytes_overflow).
3. Multi-driven nets (gtwiz_reset_qpll0reset_out, gtwiz_reset_qpll1reset_out).
I managed to compile it, but unfortunately it doesn't work as expected. Firstly, there is hardcoded loopback. It is set through axi4 lite into 31th bit of MODE_REG, address 'h0008.
After I've switched it off into _axi4_lite_user_if.v file and recompiled the example, 10G seems to work properly. But 1G doesn't. After switching into 1G, completion status is: 5'd31 Test is stuck in reset.
It is seen from debug that frequencies of the rx and tx clocks are wrong, they aren't equal expected 125 MHz.
Switching doesn't work. I suppose because signal gt_switching holds state machines in axi and gen_mon modiles into reset state.
After sys_reset, example design switches into default state 10G.
Why switching into 1G mode doesn't work?
I supposed that it is due to 10G SFP module, but it also doesn't work with enabled loopback.
Then, I thought that it is due to wrong resets, because tx_reset and rx_reset are assigned to 0 into gen_mon module. But when I added the resets from vio, it didn't help.
Have someone any ideas about how to fix this?
10-19-2018 03:24 AM
Yes, I am working with vivado 2018.2.
Unfortunately example design for 1G/10G/25G Switching Ethernet Subsystem ipcore still doesn't work.
Have you any idea what wrong with switching into 1G mode?
Or maybe, can someone post working example?
11-01-2018 10:11 AM
1G doesn't work, because CPLL doesn't be able to lock. I've checked signals CPLLPD and gtwiz_cpllreset_, they are down in 1G mode.
There are ARs about the CPLL problem:
I've checked my example design and found that the fixes from ARs are already there.
Can someone suggest how to fix the problem?
02-06-2019 12:48 AM
is there any update on this item?
I notice that 1/10/25 G switchable subsystem IP is no longer in Vivado 2018.2 IP catalog,
I can only fid it in Vivado 2018.3 release.
Anyone using it or the example design?