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Explorer
Explorer
224 Views
Registered: ‎07-01-2015

10G/25G and 40G/50G ethernet subsystem AXI interface

Hi All,

I want to use 10G/25G and 40G/50G Ethernet Subsystem. I have a doubt regarding AXI Stream interface here. We know that there is an Inter Packet Gap(IPG) defined between consecutive ethernet packet. Does this also say that there should be gap between packets coming out from MAC through AXI Stream interface or consecutive packets may come from MAC through AXI stream interface without any gap?

 

Thanks & Regards,

Musthafa V

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4 Replies
Xilinx Employee
Xilinx Employee
173 Views
Registered: ‎07-26-2012

Re: 10G/25G and 40G/50G ethernet subsystem AXI interface

On the receiving side, gaps are usually caused by deletion of IPG etc.

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Explorer
Explorer
144 Views
Registered: ‎07-01-2015

Re: 10G/25G and 40G/50G ethernet subsystem AXI interface

Hi @kurihara,

So, are you telling that there will be always gap between consecutive packets coming out from MAC ?

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Xilinx Employee
Xilinx Employee
136 Views
Registered: ‎07-26-2012

Re: 10G/25G and 40G/50G ethernet subsystem AXI interface

On RX tvalid can go low if RX axi clock is faster or due to removal of data such as alignment markers. If you can send the pattern close to the actual packets in simulation, you can see it.

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Explorer
Explorer
106 Views
Registered: ‎07-01-2015

Re: 10G/25G and 40G/50G ethernet subsystem AXI interface

Hi @kurihara,

Still am not clear about your answer. What I actually want to know is, can MAC provide consecutive packets without a gap to client. i.e. keeping tvalid high and toggling tlast.

If there is a minimum gap between consecutive packets, can you please tell what is that gap in rx_clk cycles ?

 

Thanks,

Musthafa V

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