01-25-2016 07:00 AM
Hello, I have a design with a 312.5MHz reference clock for my 10G ethernet transceiver, which works well with the 10G Ethernet subsystem core configured in 32-bit mode. I would like to use the 1588 subsystem, which is only available when the core is configured in 64-bit mode.
Would it be possible to configure the core to run in 64-bit mode, but still use a 312.5MHz reference clock for the transceiver? Would this be as simple as configuring the core with the common transceiver logic in the example design, and then modifying the settings in the gt_common_block ?
01-25-2016 07:29 AM
In fact is this as simple as setting QPLL_REFCLK_DIV to 2 instead of 1? It looks to me like that should work.
01-25-2016 08:57 AM
01-25-2016 09:39 AM
Which device are you targetting this core?
If ultrascale devices then you have a GUI option to select 312.5Mhz as reference clocks and if 7 series then you need to generated the gtwizard for 10GBASE_R protocol for 312.5Mhz as reference clocks and compare with the standard core(Which will be always generated for 156.25Mhz reference clocks) generated wizard files for the modifications need to be done.
01-25-2016 09:54 AM
It's for a Zynq 7045. I will generate the gtwizard files and compare them.