UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Reply

10G PCS/PMA RX simulation problem

Highlighted
Adventurer
Posts: 80
Registered: ‎08-26-2013

10G PCS/PMA RX simulation problem

Hi,

Using 10G PCS/PMA core in simulation, displays same good functionality same as hardware real implementation in TX side but RX side of same link including MAC and PCS/PMA core is failed during simulation and implementation. It's important that after adding RX logic(including processing received packet and links between mac & PCS/PMA etc), both TX and RX link are failed exactly and txc and rxc lines show this result too. What's the problem with my design and thanks for any hints...

 

Re

mhmontazeri61

Xilinx Employee
Posts: 2,291
Registered: ‎02-16-2010

Re: 10G PCS/PMA RX simulation problem

If you are looking to use MAC and PCS/PMA together, can you check 10G Ethernet subsystem IP (or)10G/25G Ethernet subsystem IP?
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
Moderator
Posts: 3,220
Registered: ‎02-06-2013

Re: 10G PCS/PMA RX simulation problem

Hi

 

What exactly are  you monitoring when you say RX is failing and what is the extra logic you have added when you see both Tx and RX failing.

 

Can you upload the simulation dump high lighting the issue you are seeing.

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
Observer
Posts: 20
Registered: ‎09-08-2015

Re: 10G PCS/PMA RX simulation problem

Hi ,

 

Did you monitor you reset signals? are they stable while the cable is connected to the Ethernet port? Is control signals rxc and txc are in IDLE?

Did you connect the coreclk and dclk to a free-running clock?

 

Kind regards,

Pedram Kermani

 

Adventurer
Posts: 80
Registered: ‎08-26-2013

Re: 10G PCS/PMA RX simulation problem

@venkata,

I'm during implementation of youyr mentioned cores. But my selected device does not support 25G lanes(i think).

 

Re

mhmontazeri61

Adventurer
Posts: 80
Registered: ‎08-26-2013

Re: 10G PCS/PMA RX simulation problem

@yenigal,

Below attached PNGs show RX and TX lines of my instantiated core. Results gathered by ila inserted cores. Thanks for more info.

 

Regards

mhmontazeri61

RX.PNG
TX.PNG
Adventurer
Posts: 80
Registered: ‎08-26-2013

Re: 10G PCS/PMA RX simulation problem

@pd.kermani,

My design in upstream side is exactly successful and your questions are true but seems they're not my problem at this time, though about your questions: all related signals are true and resets are inactive and two clocks are in free running normal state.

 

Re

mhmontazeri61

Moderator
Posts: 3,220
Registered: ‎02-06-2013

Re: 10G PCS/PMA RX simulation problem

Hi

 

I see remote faults transmitted on the TX which will happen when there is a local fault.

 

Below are the causes which can cause local fault which triggers the remote fault.

 

First check which of this is happening and resolve it.

 

The transceiver has not locked or the receiver is being reset.

• The block lock state machine has not completed.

• The BER monitor state machine indicates a high BER.

• The elastic buffer has over/underflowed

 

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
Adventurer
Posts: 80
Registered: ‎08-26-2013

Re: 10G PCS/PMA RX simulation problem

@yenigal,

Thanks for your reply. I'm investigating your mentioned cases and i inform about the result certainly. Some problems exist that i questioned in the other posts and some of they are without any answer yet like the reason of unlock but working my core properly.

 

Regards

mhmontazeri61

Xilinx Employee
Posts: 36
Registered: ‎05-01-2013

Re: 10G PCS/PMA RX simulation problem

What's the link partner in your test?

If you do GT near end PMA loopback, can the design work?