08-12-2017 05:26 AM
Using 10G PCS/PMA core in simulation, displays same good functionality same as hardware real implementation in TX side but RX side of same link including MAC and PCS/PMA core is failed during simulation and implementation. It's important that after adding RX logic(including processing received packet and links between mac & PCS/PMA etc), both TX and RX link are failed exactly and txc and rxc lines show this result too. What's the problem with my design and thanks for any hints...
08-16-2017 09:17 AM
08-16-2017 08:50 PM
What exactly are you monitoring when you say RX is failing and what is the extra logic you have added when you see both Tx and RX failing.
Can you upload the simulation dump high lighting the issue you are seeing.
08-18-2017 08:00 AM
Did you monitor you reset signals? are they stable while the cable is connected to the Ethernet port? Is control signals rxc and txc are in IDLE?
Did you connect the coreclk and dclk to a free-running clock?
08-19-2017 03:31 AM
My design in upstream side is exactly successful and your questions are true but seems they're not my problem at this time, though about your questions: all related signals are true and resets are inactive and two clocks are in free running normal state.
08-20-2017 05:08 AM
I see remote faults transmitted on the TX which will happen when there is a local fault.
Below are the causes which can cause local fault which triggers the remote fault.
First check which of this is happening and resolve it.
The transceiver has not locked or the receiver is being reset.
• The block lock state machine has not completed.
• The BER monitor state machine indicates a high BER.
• The elastic buffer has over/underflowed
08-20-2017 10:53 PM
Thanks for your reply. I'm investigating your mentioned cases and i inform about the result certainly. Some problems exist that i questioned in the other posts and some of they are without any answer yet like the reason of unlock but working my core properly.