05-28-2019 05:14 PM
I am having a problem where the 10GE subsystem TX suddenly stops sending data. This very repeatably occurs after 11h 4m of continuous operation. I have measured the time to failure 5 times and they are all within about 30ms of each other.
I am using Vivado 2018.2. The FPGA is Kintex7 XC7K420T.
I am operating 8 10GE subsystems, they all stop at the same time, as far as I can tell. Everything on the Host PC side seems fine up to this point. The 8 subsystems are configured in sets of 4, sharing a GT quad as shown in Figure 3-66 here: https://www.xilinx.com/support/documentation/ip_documentation/axi_10g_ethernet/v3_1/pg157-axi-10g-ethernet.pdf
The two quads share a single reference clock through the transceiver clock routing features.
I am sending 8258-byte jumbo frames. The packet rate is 117187.5 packets per second.
I attached a screenshot from where the failure occurs. I have broken out the size and bytes fields from the tx_statistics_vector. You can see in the middle of the packet, bytes goes to 0 and the packet size counter stops counting up. I cannot figure out what causes this. The AXI bus continues to accept data, does not deassert the tready signal.
What can cause this behaviour?
05-29-2019 12:46 AM
What is the licensing type for this core. Please find the below snippet from PG157 which highlights the behaviour of the core:
05-29-2019 10:16 AM
Thanks. I was told that we have the license for this IP. Looking at the log, it says
icejagfpga.runs/impl_1/icejag_top.vdi: IP core 'bd_91a5_xmac_0' (ten_gig_eth_mac_v15_1_6) was generated using a design_linking license.
icejagfpga.runs/impl_1/icejag_top.vdi: IP core 'bd_91a5_xpcs_0' (ten_gig_eth_pcs_pma_v6_0_13) was generated using a design_linking license.
icejagfpga.runs/impl_1/icejag_top.vdi: IP core 'bd_083c_xmac_0' (ten_gig_eth_mac_v15_1_6) was generated using a design_linking license.
icejagfpga.runs/impl_1/icejag_top.vdi: IP core 'bd_083c_xpcs_0' (ten_gig_eth_pcs_pma_v6_0_13) was generated using a design_linking license.
But AR42379 https://www.xilinx.com/support/answers/42379.html indicates that Design-Linking License is synonymous with Simulation-Only License and that you cannot generate a bitstream for this design.