12-06-2018 07:44 AM
I am trying to figure out how to connect a DDR3 with AXI4 interface to an AXI interconnect block. The system is running at 160 MHz, however, the DDR3 interface is running at 133 MHz. This rate is due to running the DDR3 memory at 533MHz and the user clock is set to 1/4 of this clock rate (or 133MHz).
The figure below shows my configuration. I see that using clock crossing I can cross at integer ratios (1:2, 1:3, etc.), however, I wasn't sure if the interconnect was able to cross at these rates using the Interconnect FIFO option. All the data is 256-bits wide. Can someone tell me if this is a viable solution using the Interconnect FIFO option? How would I set up the interconnect block to implement this?
12-06-2018 09:56 AM
The AXI Interconnect IP already has a Clock Conversion feature. You should be able to enable it, and it will instantiate a few asynchronous FIFOs in the logic to store and froward the data.
According to the document AXI Interconnect Product Guide v2.1 - PG059, pg. 90:
Clock conversion can be performed in any of the following ways. • Synchronous clock-rate acceleration (1:N), where the MI-side clock rate is an edge-aligned integer multiple of the SI-side clock rate. • Synchronous clock-rate reduction (N:1), where the SI-side clock rate is an edge-aligned integer multiple of the MI-side clock rate. • Asynchronous clock rate conversion either accelerates or reduces clock rate by passing the signals of each channel through an asynchronous FIFO. When the tools determine that the relationship between an interface and the crossbar is an integer ratio (faster or slower) within the range 1:16 to 16:1, the tools automatically configure the Clock Converter to perform synchronous conversion; otherwise, the Clock Converter is configured in asynchronous mode.
Please also take a look on page 133 for more information on how to configure the AXI Clock Converter.
12-06-2018 11:28 AM
Thanks for your reply. However, I don't see any enable for a clock crossing feature. To test this I instantiated an AXI interconnect block as shown below. The slave ports all run off the ACLK (160MHz) while the master ports on the left run off M00_ACLK (200MHz). I am sending data from a master connected to port S01 through to a DDR connected to port M00.
NOTE: I am testing on an evaluation board so the M00_ACLK is 200MHz in this setup not the 133MHz I will have in the final product. The idea is the same, I want to test how interconnect handles the different clock domains.
I would expect all the signals on the M00/M01 side to be synchronized to the 200MHz (fabric_clk in figure below) but they are not. You can see AWVALID is synchronized to the 160MHz clock.
You said the interconnect will generate the appropriate FIFO's to make the path work. However, the interface is not working as it does not send anything more after the first data word. The BREADY does not make it through the interconnect to the sending master connected to port S01.
12-06-2018 11:38 AM
Here, you can see the data is still synchronous to the 160MHz clock NOT the 200MHz clock as I would expect.
12-07-2018 01:27 PM
I just checked and although it's all treated within the same IP document, there's an actual separate IP for clock conversion, called AXI Clock Converter.
So you might need to manually instantiate, configure and connect them, and it should be able to work now.