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Newbie paulmtcuk
Newbie
250 Views
Registered: ‎01-29-2019

Artix-7 Auroa8b10b tx_hard_err always high

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 am a Vivado newbie and trying to simulate the aurora 8b10b with it. The problem is that with all simulations, tx_hard_err remains high from start up and doesn't change. This design doesn't actually clock and data yet, in my designs that actually clocked in data nothing would happen which I assume is caused by the tx_hard_err issue. The design is below and the clk_in is off the screen to the left.

design.JPG

 

I've just been trying to get tx_hard_err to reset, even by asserting gt_reset by forcing it constant in the simulator for 140ns (at least 6 x 50Mhz clock cycles) and tx_hard_err doesn't change. I've also tried via VHDL and test bench from initialisation with no success either.

sim.JPG

 

Just wondering if this is an Artix-7 thing only?

Chosen device is xc7a50tfgg484-1

 

the core is designed as TX simplex only

 core.JPG

PS., I notice that the auto INIT / DRP clk appear to change from time to time ? updating the clock inputs don't appear to help anyway

Thanks for any advice!

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Newbie paulmtcuk
Newbie
100 Views
Registered: ‎01-29-2019

Re: Artix-7 Auroa8b10b tx_hard_err always high

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Okay thanks,

turns out tx_hard_err would reset after 53 us. (which is an eternity in Simulation time).

Although tready would never go high in simulation (I assume it would take an even longer eternity), in actual hardware it works fine.

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Voyager
Voyager
211 Views
Registered: ‎02-01-2013

Re: Artix-7 Auroa8b10b tx_hard_err always high

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Reset needs to be held for 6 user_clk cycles; you're not even getting user_clk out of the core yet.

Try it without asserting powerdown.

-Joe G.

 

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Newbie paulmtcuk
Newbie
185 Views
Registered: ‎01-29-2019

Re: Artix-7 Auroa8b10b tx_hard_err always high

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Hi, I've been going with the assumption from reading "Aurora 8B/10B v11.0" document

During power-on, the gt_reset and reset signals of both the TX simplex and RX simplex cores are expected to be High

The assertion time of gt_reset must be a minimum of six init_clk time periods

I've created a driver to do this and load data, but tx_hard_err remains high from start-up (power_down is deasserted).

sim2.JPG

any more help is appreciated.

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Voyager
Voyager
169 Views
Registered: ‎02-01-2013

Re: Artix-7 Auroa8b10b tx_hard_err always high

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user_clk is not init_clk or drp_clk. You still don't have user_clks coming out, so the core hasn't finished resetting yet. That's one of the reasons TREADY and sys_reset_out are still unknown--and tx_hard_err is still high.

Have you checked out the Simulation section of UG476, as well as UG626?

-Joe G.

P.S.  Why are you sending data into the AXI Stream, when TREADY is not high? You should fix that.

 

 

Newbie paulmtcuk
Newbie
101 Views
Registered: ‎01-29-2019

Re: Artix-7 Auroa8b10b tx_hard_err always high

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Okay thanks,

turns out tx_hard_err would reset after 53 us. (which is an eternity in Simulation time).

Although tready would never go high in simulation (I assume it would take an even longer eternity), in actual hardware it works fine.

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