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Scholar jprice
Registered: ‎01-28-2014

Aurora 8b10b v10.1 Issue


   I have 4 Aurora independent lanes (8b10b) connected between a Zynq (7045) and a Virtex 7 (485t). Both parts are -1 speed grade. The core is configured as a streaming core running at 6.25 gbps. I have a rare startup issue that can affect any of the lanes. The issue that some time after comnig out of reset (hundreds of clock cycles) there is a chance that the Rx side will see a word that was not sent by its corresponding Tx side.  The issue is relatively rare and is always a single word. I can't find anything that explains this. I don't think it is some sort of logic bug since this issue happens without absolutely no data being fed into the core (I disconnected the Tx enable). If anyone has any insight that would be much appreciated!


Thank you very much.



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Registered: ‎02-16-2010

Re: Aurora 8b10b v10.1 Issue

Have you captured the word being received? By Tx enable, do you mean s_axi_tx_tvalid signal?

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