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Visitor smoky
Visitor
4,585 Views
Registered: ‎06-10-2010

Aurora 8b10b v8.3 CRC issue

Hello,

 

i am using Vivado 14.4 and Aurora 8b10b v8.3 with the following configurations:

 

UFC+NFC immediately

ref. clk: 132MHz

lanes: 4

lane width: 4 bytes

line rate: 6.6 Gb/s

CRC: on

duplex

framing

 

The concatenation of the lane CRC sum (for more than 1 lane) in "aurora_8b10b_txcrc.v/.vhd" and "aurora_8b10b_rxcrc.v/vhd" are differently.

 

TXCRC line 314:

 

assign final_CRC = {
        CRC4 ,
        CRC3 ,
        CRC2 ,
        CRC1 };

 

RXCRC line 289:

 

assign final_CRC = {
                      CRC1,
                      CRC2,
                      CRC3,
                      CRC4 };

 

Thes results in an wrong CRC check.

 

RXCRC line 363 :

 

assign CRC_PASS_FAIL_N  = (received_CRC == final_CRC);

 

Please correct my if i am wrong.

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5 Replies
Visitor jenyman
Visitor
4,378 Views
Registered: ‎07-18-2013

Re: Aurora 8b10b v8.3 CRC issue

I have the same problem as you, and have opened a Webcase concerning this issue.

Its not only the concatenation that is (possibly) wrong, the checking of REM_US in txcrc/rxcrc is also faulty(I think), thus the CRC when using a TKEEP that is not only 'ones' will also be faulty.

 

Try changing the output data from the frame generator included in the example design, so that the data on every lane is not the same. This will cause the included testbench to fail.

 

 

 

 

 

 

 

 

 

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Moderator
Moderator
4,261 Views
Registered: ‎02-16-2010

Re: Aurora 8b10b v8.3 CRC issue

Do you reproduce the issue in simulation? is this with example design?
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Visitor jenyman
Visitor
4,173 Views
Registered: ‎07-18-2013

Re: Aurora 8b10b v8.3 CRC issue

Yes. Try changing the frame_gen and frame_check code in the example design to not always transmit and receive the same data on all (in this case) four channels.

 

 

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Visitor jenyman
Visitor
4,171 Views
Registered: ‎07-18-2013

Re: Aurora 8b10b v8.3 CRC issue

These are the changes i did to the fram_gen and frame_check files. The line numbers are unfortunately missing but the lines changed are almost in the middle of both pictures. The original lines are commented.

 

The new (faulty) behaviour is shown in the modelsim screencap below.  The correct data arrives but the crc flags says the checksum is faulty. emacs.pngvsim.png

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Visitor jenyman
Visitor
4,168 Views
Registered: ‎07-18-2013

Re: Aurora 8b10b v8.3 CRC issue

right click -> view image for full size.

 

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