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Scholar golson
Scholar
5,095 Views
Registered: ‎04-07-2008

Aurora Clock Correction Demo Design Mistake 13.2 ISE.

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I believe there is a mistake in the Aurora Streaming and Packet Example Designs when it comes to the DO_CC signal.

 

That is the module instantiation as corrected :

 

cc_while_lane_up <= NOT lane_up_i;

standard_cc_module_i : aurora_STANDARD_CC_MODULE

port map

(

-- Clock Compensation Control Interface

WARN_CC => warn_cc_i,

DO_CC => do_cc_i,

-- System Interface

PLL_NOT_LOCKED => pll_not_locked_i,

USER_CLK => user_clk_i,

RESET => cc_while_lane_up --lane_up_reduce_i

);

 

 

The reset of the module was held high during  active LANE UP originally.  This prevented clock correction

from running until the Lane went down.  After inverting the reset signal  Clock Correction started working

periodically.  It now does not exibit overrun underrun errors which I was getting before the change.

 

 

   

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Scholar golson
Scholar
8,104 Views
Registered: ‎04-07-2008

Re: Aurora Clock Correction Demo Design Mistake 13.2 ISE.

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This Problem is solved.

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Scholar golson
Scholar
8,105 Views
Registered: ‎04-07-2008

Re: Aurora Clock Correction Demo Design Mistake 13.2 ISE.

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This Problem is solved.

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