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Visitor ssh24
Visitor
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Registered: ‎02-26-2019

BD 41-237 Bus Interface Property FREQ_HZ does not match

I am using a Tri Mode Ethernet MAC along with a AXI direct memory access in my design.

When I have my design ready I run Synthesis which fails due to the errors listed below:

  • [BD 41-237] Bus Interface property FREQ_HZ does not match between /tri_mode_ethernet_mac_0/s_axis_tx(125000000) and /axi_dma_0/M_AXIS_MM2S(100000000)
  • [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /tri_mode_ethernet_mac_0/s_axis_tx(/clk_wiz_clk_out1) and /axi_dma_0/M_AXIS_MM2S(design_1_processing_system7_0_0_FCLK_CLK0

I tried changing the properties but its read only. Also the result is not reflected after changing the xml and xci files.

Awaiting your suggestions

Thank you

 

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