02-20-2018 01:52 PM
I finally could generate the bitcode of the UltraScale+ 100G Ethernet Subsystem example design for VCU118 using the following setting:
Mode: CAUI4 - Simplex TX
GT RefClk: 161.1328
**Disabled** Include AXI4-Lite Control and Statistics Interface
CMAC Lane to Transceiver: CMACE4 X0Y7 [X1Y48~X1Y51] to use GT for QSFP1
and this is the constraint file:
create_clock -period 10.000 [get_ports init_clk_p]
create_clock -period 6.206 [get_ports gt_ref_clk_p]
set_property PACKAGE_PIN AY24 [get_ports init_clk_p] # CLK_125MHZ_P
set_property PACKAGE_PIN W9 [get_ports gt_ref_clk_p] # QSFP_SI570_CLOCK_C_P - MGTREFCLK0P_231
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports init_clk_n]
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports init_clk_p]
set_property IOSTANDARD LVCMOS18 [get_ports sys_reset]
set_property IOSTANDARD LVCMOS18 [get_ports send_continuous_pkts]
set_property IOSTANDARD LVCMOS18 [get_ports lbus_tx_rx_restart_in]
set_property IOSTANDARD LVCMOS18 [get_ports simplex_mode_rx_aligned]
set_property IOSTANDARD LVCMOS18 [get_ports tx_done_led]
set_property IOSTANDARD LVCMOS18 [get_ports tx_busy_led]
set_property IOSTANDARD LVCMOS18 [get_ports tx_gt_locked_led]
### Any other constraints can be added here
set_false_path -to [get_pins -leaf -of_objects [get_cells -hier *cdc_to* -filter is_sequential] -filter NAME=~*cmac_cdc*/*/D]
set_property PACKAGE_PIN AV34 [get_ports tx_busy_led] #GPIO-LED
set_property PACKAGE_PIN AY30 [get_ports tx_done_led] #GPIO-LED
set_property PACKAGE_PIN BB32 [get_ports tx_gt_locked_led] #GPIO-LED
set_property PACKAGE_PIN BD23 [get_ports sys_reset] #GPIO-Switch
set_property PACKAGE_PIN BE22 [get_ports simplex_mode_rx_aligned] #GPIO-Switch
set_property PACKAGE_PIN BF22 [get_ports send_continuous_pkts] #GPIO-Switch
set_property PACKAGE_PIN BB24 [get_ports lbus_tx_rx_restart_in] #GPIO-Switch
It *seems* it is working because the LEDs change status according to the documentation, I intend to capture the packets with WireShark or similar tools. The problem is that the 100G Infiniband Switch which QSFP1 is connected by Ethernet cable to does not show the interface *up* and Ethernet LEDs are not ON.
According to the QSFP datasheet, they are connected to vcc and should be on. so why the interface is not up? How to bring QSFP interface up/down?
02-23-2018 08:35 AM
I tried with several QSFP interfaces, I'm pretty sure when I connect two QSFP interfaces, a green light should flash slowly when there is no data flowing.
I would be grateful if someone please help me why this does not happen with my VCU118 board.
As I mentioned in the previous post, I have checked the schematics, I didn't see any jumper or switch to turn on the QSFP.
02-27-2018 12:03 PM
By default the Si570 clock will run at 156.25Mhz, have you used system controller to check the frequency of this clock and change to 161.xMhz?
For debug purposes, it would be helpful to generate CMAC for both RX and TX operation and check if you are able to get link up and send traffic in near-end PMA loopback and optical cable loopback.
02-28-2018 08:55 AM - edited 02-28-2018 09:00 AM
@ejanney yes. As you suggested I enabled Duplex mode to do some debugging. However, I cannot get the link up.
The frequencies of the board is as following
Si570_2 161.1328125 MHz
I have connected the init_clk to CLK_125MHZ and in 100G IP core wizard "GT DRP/init Clock" is set to 100.00.
Lane Rates are 25.78125Gb/s and PLL types for Transmitter and Receiver is QPLL0.
02-28-2018 09:04 AM - edited 02-28-2018 09:16 AM
And also, It might be necessary to mention that, I have done simulations and they are successful, so I'm sure the algorithm is working.
When I load the bitcode to the fpga, rx_gt_locked_led will turn on.
02-28-2018 01:52 PM
03-02-2018 11:35 AM
Can you check the output of the QSFP (or the terminal of the fiber) with a detector card? Some modules need a command from the I2C interface to wake up from low power mode.
If they are not in low power mode, they get a little bit warm. Are your modules cold?
Also check your clocks with an oscilloscope, if they are running, AFTER programming. In my board, some reset inputs are driven from the FPGA. The latter drives the unused ports to low (default setting) when programmed, so many of the surrounding ICs get their NRST pin asserted and stuck in reset.
You can drive these reset pins into HIGH with your code, or change the setting of the unused pins from low to floating or Hi-Z. (Open an implemented design and go to Bitstream -> Configure additional bitstream properties -> Configuration and change the setting Unused IOB pins to PULLNONE).
Hope that all these might help you
03-05-2018 09:42 AM
@ttzotzarosThank you. I haven't followed your guidance yet, but I can say that my modules are cold, they do not get warm. So it seems they are in low power mode.
I'll update this thread as soon as I followed your suggestions.
03-09-2018 08:18 AM