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10,827 Views
Registered: ‎05-23-2014

CPRI example design implementation

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Hi everyone,

 

I am new to CPRI and GTX related designs, so please forgive any silly question I going to ask.

 

I am working on the CPRI example design, with a Kintex 7 FPGA.

After creating the example design and running the tests suggested on the product guide, I am trying to implement the same example design on the FPGA, but I am having some trouble:

- I created a new IP, packaging the entire example design, with GTX serial outputs (txp, txn) connected to the same GTX serial inputs (rxp, rxn), as suggested on the "Test Bench" section of the Product Guide.

- I added the newly created IP on a new block design

When I try to Run Implementation I get a Critical Warning saying:

"2 net(s) are unrouted. The problem net(s) are <component_name>/txn, <component_name>/txp".

 

What is this problem due to?

Is it possible to connect the GTX serial outputs to the same GTX serial input ports?

 

Thanks

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Scholar kotir
Scholar
17,331 Views
Registered: ‎02-03-2010

Re: CPRI example design implementation

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Hi Gabelli,

 

 

The core pin out can not be looped back at differential signals. i.e., you shoud not assign txp to rxp and txn to rxn inside the toplevel file. This is not routable inside the FPGA.

 

You need to do implement the design with txp/n and rxp/n to Transceiver I/Os on to the SMA connector or any cable to loop back the data on to Rx side.

 

Let me know if this is clear now.

 

Regards,

KR

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8 Replies
Xilinx Employee
Xilinx Employee
10,824 Views
Registered: ‎07-11-2011

Re: CPRI example design implementation

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HI

 

What exactly you mean by "Is it possible to connect the GTX serial outputs to the same GTX serial input ports?"

 

Do you mean by loop back? Can you share your pin assignements?

 

For proper loop back please refer Page - 90 of below UG.

 

http://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf

 

 

Regards,

Vanitha

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Xilinx Employee
Xilinx Employee
10,818 Views
Registered: ‎02-06-2013

Re: CPRI example design implementation

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Hi

 

The TX>RX cannot be done inside the core but you can do the RX->TX loopback if you want because TXP and Txn are output pins and Rxp and Rxn are input pins from the Transceiver..

 

The test bench is only for simulation and it is not synthesizable.

 

If you can share more details of your application core configuration(Master or slave ) and what exactly you want to test then

 

We can give you more suggestions.

Regards,

Satish

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10,764 Views
Registered: ‎05-23-2014

Re: CPRI example design implementation

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Hi Vanitha, thanks for your answer.

 

Yes, I mean by loop back.

 

Actually, I did not assign any PIN to the GTX transceiver.

 

What I was thinking to do is creating the loop back by VHDL assigning:

rxp <= txp

rxn <= txn

(txn, txp. rxn, rxp are the names used in the CPRI example design)

 

Is it allowed?

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Xilinx Employee
Xilinx Employee
10,761 Views
Registered: ‎02-06-2013

Re: CPRI example design implementation

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Hi

 

This is not possible.

 

See my above reply for the same..

Regards,

Satish

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10,758 Views
Registered: ‎05-23-2014

Re: CPRI example design implementation

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Hi, thanks for your answer.

 

"The TX>RX cannot be done inside the core but you can do the RX->TX loopback if you want because TXP and Txn are output pins and Rxp and Rxn are input pins from the Transceiver" ?

 

I tried to connect the transceiver pins in VHDL ( CPRI core example design pin names )

rxn <= txn

rxp <= txp

According to what you said it should be allowed. Am I correct??

 

If you can share more details of your application core configuration(Master or slave ) and what exactly you want to test then we can give you more suggestions.

 

I am trying to test on the FPGA the example design (with the core configured as Master) provided with the CPRI core:

data are generated, transmitted and received from the same core, connected in a loopback configuration, and finally checked.

 

thanks ..

 

 

 

 

 

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Scholar kotir
Scholar
17,332 Views
Registered: ‎02-03-2010

Re: CPRI example design implementation

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Hi Gabelli,

 

 

The core pin out can not be looped back at differential signals. i.e., you shoud not assign txp to rxp and txn to rxn inside the toplevel file. This is not routable inside the FPGA.

 

You need to do implement the design with txp/n and rxp/n to Transceiver I/Os on to the SMA connector or any cable to loop back the data on to Rx side.

 

Let me know if this is clear now.

 

Regards,

KR

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10,750 Views
Registered: ‎05-23-2014

Re: CPRI example design implementation

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This is the answer I was looking for! Thanks a lot!

 

Last question, just to have ideas completely clear:

where can I find some references about this?

I was looking exactly for a reference saying that the pins are not routable inside the FPGA but I could not find anything clear to this regard.

 

Could you please suggest some documents?

 

thanks!

 

 

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Scholar kotir
Scholar
10,736 Views
Registered: ‎02-03-2010

Re: CPRI example design implementation

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Hi ,

 

check the architecture of MGT blocks. the black circles are fpga fabric interface. i.e., signals at this point are accessible for FPGA.

 

Part Left to the FPGA is all hard block (MGT). those are not routable by FPGA tools.

 

the red cicles are the place where the differential pins are placed over device.

 

I hope its clear you now.

 

gt.png

 

Regards,

KR

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