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Participant mr-read
Participant
1,883 Views
Registered: ‎11-27-2017

CPRI loopback with two FPGAs

Hello,

I am trying to setup a CPRI loopback with two FPGAs connected via SFP. I am using the ZCU102 evaluation boards and I would like to have one board configured for simple loopback. I have tried tying all IQ, Vendor Specific, HDLC, and Ethernet signals together (Rx=>Tx) but I see bit errors and I am unsure if I have the correct signals routed. I have tried using the reference designs in the CPRI lounge, but they are designed for external loopback (SFP) not internal loopback. The reference design should work fine for the master bitfile, but not the loopback. Also, I tried building the CPRI Master-Slave demo but it includes a version of the VCU board that I cannot find in Vivado part library.

 

---update: I am only seeing bit errors on IQ and Ethernet, not HDLC or Vendor Specific data. I do see counters increasing for all data however.

 

Desired setup:

 

Board 1: Master

Board 2: Loopback

 

CPRI Stimulus -> CPRI Core(Tx) -> SFP(Tx) -> (To Board 2)

 

(From Board 1) -> SFP(Rx) -> CPRI Core(Rx) -> CPRI Core(Tx) -> SFP(Tx) -> (To Board 1)

 

(From Board 2) -> SFP(Rx) -> CPRI Core(RX) -> CPRI Checker

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13 Replies
Participant mr-read
Participant
1,849 Views
Registered: ‎11-27-2017

Re: CPRI loopback with two FPGAs

To clarify, I am currently connecting the following pairs of TX/RX signals in the loopback FPGA:

 

iq_tx => iq

iq_rx => iq

 

vendor_tx_data => vendor_data

vendor_rx_data => vendor_data

 

nodebfn_tx_strobe => nodebfn_strobe

nodebfn_rx_strobe => nodebfn_strobe

 

nodebfn_tx_nr => nodebfn_nr

nodebfn_rx_nr => nodebfn_nr

 

eth_txd => eth_data

eth_rxd => eth_data

 

eth_tx_er => eth_er

eth_rx_er => eth_er

 

eth_tx_en => eth_en_dv

eth_rx_dv => eth_en_dv

 

eth_rx_avail  => eth_avail_rdy

eth_tx_ready => eth_avail_rdy

 

hdlc_rx_data => hdlc_data

hdlc_tx_data => hdlc_data

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

Re: CPRI loopback with two FPGAs

@mr-read Can you let me know the revision of ZCU102 board, please? Also please attach the top level of your design. For internal loopback, you need to change three bits loopback settings, as per GT requirement, which value do you use?

loopback.JPG

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Participant mr-read
Participant
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Registered: ‎11-27-2017

Re: CPRI loopback with two FPGAs

Hello @xud,

 

We are using rev 1.1 ZCU102 boards and I have attached the top level of the current loopback design. 

 

I have the simple version of our loopback working now, but I had to delay the IQ data one more clock than the other CPRI components (Vendor Specific, Ethernet, etc.) which I don't understand.

 

To clarify, we are trying to loopback the data in the CPRI domain not at the transceivers. Eventually we will be transmitting only a portion of the IQ data and control words and this was the first step. The next step will be to add a master CPRI core and loop the CPRI data from an external BERT into the CPRI slave to the CPRI master back out to the BERT.

Specific questions are why did IQ data need to be delayed one clock and are there any design considerations I need to make when connecting the CPRI slave to the CPRI master for an external BERT CPRI loopback?

 

Thanks,
Jordan

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

Re: CPRI loopback with two FPGAs

@mr-read I have downloaded and generated 2017.3 ZCU102 hardware demo, I will do some tests tomorrow, and then let you know how it goes.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

Re: CPRI loopback with two FPGAs

@mr-read

 

I think I know why you are seeing one cycle difference. When you mention internal loopback, it doesn't refer to txp/n-rxp/n internally. It means you connect nodebfn_tx_strobe to nodebfn_rx_strobe, and nodebfn_tx_nr to nodebfn_rx_nr.

 

From Figure 3-46 and Figure 3-48, the nodebfn_tx_strobe/iq_tx_enable and basic_frame_first_word/nodebfn_rx_strobe timings are similar.

 

However the first iq_rx control word is received right before the falling edge of basic_frame_first_word, the first iq_tx control word is transmitted right after falling edge of iq_tx_enable, so it has one cycle difference.

 

iq_rx.GIF

iq_tx.GIF

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Participant mr-read
Participant
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Registered: ‎11-27-2017

Re: CPRI loopback with two FPGAs

@xud

 

That does make sense, thank you for the explanation. I am currently trying to complete the CPRI loopback with the E-EUTRA module but I can't get the decimated rx I/Q signals to sample at the correct time.

 

As shown in the attached screenshot the iq_rx(31:0) input is arriving 4 clocks after basic_frame_first_word goes high, per CPRI RATE 7 spec. However, the e-utra module is sampling the data 2 clocks after basic_frame_first_word goes high. I have tried delaying the basic_frame_first_word signal into the e-utra module, offsetting the start bit for rx samples, and both at the same time but I only see fewer samples (see second attached screenshot). I have included my current top level code, as well as my modified e-eutra modules.

 

One thing I am confused by is the number of times various generics are set and which ones are actually used? For example, in the rx_iq.vhd module the width of rx_i and rx_q is set to 20 and the startbit is set to 80, but in iq_module.vhd where it is called these are set to 10 and the relevant start bit defined in the generic above, which is also mapped in the iq_module_eutra.vhd. It is very unclear which values need to be set and where.

 

 

Although I am currently trying to make the module work with the default values (two channels, width of 10 bits, 3x oversampled), we want to take a single 20MHz channel @ rate-7 that is 15-bit sampled using AxC Mapping Method 1 and loop it through the core; I would assume that would mean the following parameters are set in iq_module_eutra.vhd: 

 

C_TX_WIDTH_1 := 15;

C_TX_S_1          :=   1;

C_TX_START_1 :=   0;

C_RX_WIDTH_1 := 15;

C_RX_S_1          :=   1;

C_RX_START_1 :=   0;

(all other values are set to 0) 

E-UTRA_RX_Input_VS_Output.PNG
Reduced_Samples.PNG
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Participant mr-read
Participant
1,628 Views
Registered: ‎11-27-2017

Re: CPRI loopback with two FPGAs

@xud

 

That does make sense, thank you for the explanation. I am currently trying to complete the CPRI loopback with the E-EUTRA module but I can't get the decimated rx I/Q signals to sample at the correct time.

 

As shown in the attached screenshot the iq_rx(31:0) input is arriving 4 clocks after basic_frame_first_word goes high, per CPRI RATE 7 spec. However, the e-utra module is sampling the data 2 clocks after basic_frame_first_word goes high. I have tried delaying the basic_frame_first_word signal into the e-utra module, offsetting the start bit for rx samples, and both at the same time but I only see fewer samples (see second attached screenshot).

 

One thing I am confused by is the number of times various generics are set and which ones are actually used? For example, in the rx_iq.vhd module the width of rx_i and rx_q is set to 20 and the startbit is set to 80, but in iq_module.vhd where it is called these are set to 10 and the relevant start bit defined in the generic above, which is also mapped in the iq_module_eutra.vhd. It is very unclear which values need to be set and where.

 

 

Although I am currently trying to make the module work with the default values (two channels, width of 10 bits, 3x oversampled), we want to take a single 20MHz channel @ rate-7 that is 15-bit sampled using AxC Mapping Method 1 and loop it through the core; I would assume that would mean the following parameters are set in iq_module_eutra.vhd: 

 

C_TX_WIDTH_1 = 15

C_TX_S_1          =   1

C_TX_START_1 =   0

C_RX_WIDTH_1 = 15

C_RX_S_1          =   1

C_RX_START_1 =   0

(all other values are set to 0) 

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Participant mr-read
Participant
1,646 Views
Registered: ‎11-27-2017

Re: CPRI loopback with two FPGAs

@xud

 

That does make sense, thank you for the explanation. I am currently trying to complete the CPRI loopback with the E-EUTRA module but I can't get the decimated rx I/Q signals to sample at the correct time.

 

As shown in the attached screenshot the iq_rx(31:0) input is arriving 4 clocks after basic_frame_first_word goes high, per CPRI RATE 7 spec. However, the e-utra module is sampling the data 2 clocks after basic_frame_first_word goes high. I have tried delaying the basic_frame_first_word signal into the e-utra module, offsetting the start bit for rx samples, and both at the same time but I only see fewer samples (see second attached screenshot).

 

One thing I am confused by is the number of times various generics are set and which ones are actually used? For example, in the rx_iq.vhd module the width of rx_i and rx_q is set to 20 and the startbit is set to 80, but in iq_module.vhd where it is called these are set to 10 and the relevant start bit defined in the generic above, which is also mapped in the iq_module_eutra.vhd. It is very unclear which values need to be set and where.

 

 

Although I am currently trying to make the module work with the default values (two channels, width of 10 bits, 3x oversampled), we want to take a single 20MHz channel @ rate-7 that is 15-bit sampled using AxC Mapping Method 1 and loop it through the core; I would assume that would mean the following parameters are set in iq_module_eutra.vhd:

 

C_TX_WIDTH_1 := 15;

C_TX_S_1          :=   1;

C_TX_START_1 :=   0;

C_RX_WIDTH_1 := 15;

C_RX_S_1          :=   1;

C_RX_START_1 :=   0;

(all other values are set to 0)

E-UTRA_RX_Input_VS_Output.PNG
Reduced_Samples.PNG
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Participant mr-read
Participant
1,666 Views
Registered: ‎11-27-2017

Re: CPRI loopback with two FPGAs

 

@xud

 

That does make sense, thank you for the explanation. I am currently trying to complete the CPRI loopback with the E-EUTRA module but I can't get the decimated rx I/Q signals to sample at the correct time.

 

As shown in the attached screenshot the iq_rx(31:0) input is arriving 4 clocks after basic_frame_first_word goes high, per CPRI RATE 7 spec. However, the e-utra module is sampling the data 2 clocks after basic_frame_first_word goes high. I have tried delaying the basic_frame_first_word signal into the e-utra module, offsetting the start bit for rx samples, and both at the same time but I only see fewer samples (see second attached screenshot).

E-UTRA_RX_Input_VS_Output.PNG
Reduced_Samples.PNG
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Participant mr-read
Participant
1,243 Views
Registered: ‎11-27-2017

Re: CPRI loopback with two FPGAs

One thing I am confused by is the number of times various generics are set and which ones are actually used? For example, in the rx_iq.vhd module the width of rx_i and rx_q is set to 20 and the startbit is set to 80, but in iq_module.vhd where it is called these are set to 10 and the relevant start bit defined in the generic above, which is also mapped in the iq_module_eutra.vhd. It is very unclear which values need to be set and where.

  

Although I am currently trying to make the module work with the default values (two channels, width of 10 bits, 3x oversampled), we want to take a single 20MHz channel @ rate-7 that is 15-bit sampled using AxC Mapping Method 1 and loop it through the core; I would assume that would mean the following parameters are set in iq_module_eutra.vhd:

 

C_TX_WIDTH_1 := 15; --15 bit sampled 20MHz channel data

C_TX_S_1          :=   8; --there are 8 sequential AxC blocks at rate 7 for 20MHz channel with 15 bit sampling

C_TX_START_1 :=   0;

C_RX_WIDTH_1 := 15; --15 bit sampled 20MHz channel data

C_RX_S_1          :=   8; --there are 8 sequential AxC blocks at rate 7 for 20MHz channel with 15 bit sampling

C_RX_START_1 :=   0;

(all other values are set to 0)

 

BTW, I've seen a related topic (https://forums.xilinx.com/t5/Networking-and-Connectivity/CPRI-AxC-MAPPING-for-eutra-20Mhz-2x2-Mimo/m-p/831504/highlight/true#M12191) but I didn't see that a solution was reached.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

Re: CPRI loopback with two FPGAs

@mr-read

 

The signal name in screenshot is too small, can you export ILA data by using File -> Export -> Export ILA data, and then attach the captured ILA data to this thread? Thanks

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Participant mr-read
Participant
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Registered: ‎11-27-2017

Re: CPRI loopback with two FPGAs

@xud

 

To better match my CPRI BERT hardware I have switched to a single 20MHz channel at Rate 7 with 15 bit sampling using Mapping Method 1. The 32-bit IQ data is currently set to 0xAAAAAAAA (1010....). I have changed the generic parameters in the iq_modules to match this setup and attached the current iq_module_eutra.vhd file I am working on.

 

There are four captures attached with the following differences:

capture 1: basic_frame_first_word direct from CPRI core output, 0-bit start offset

capture 2: basic_frame_first_word direct from CPRI core output, 30-bit start offf

capture 3: bffw (basic_frame_first_word delayed 1 clock), 0-bit start offset

capture 4: bffw (basic_frame_first_word delayed 1 clock), 30-bit start offset

 

I don't see any difference when I add a 30-bit offset but the delayed bffw looks like it's pushing the data in the right direction?

 

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

Re: CPRI loopback with two FPGAs

@mr-read

 

For line rate 9.8G, it's expected to have 4 cycles for control words. It has been documented in PG056

9_8G.GIF

 

After you change the generic parameters, please use iq_rx_data_valid_n to judge if data is value or not. As you can see in the figure below, data won't be transferred if iq_rx_data_valid_n is de-asserted

e_utra.GIF

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