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449 Views
Registered: ‎06-04-2018

CPRI v8.8 PMA Loopback and Physical Loopback fail on ZCU102 in Vivado 2017.4

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Hi community,

 

I want to implement on the ZCU 102 FPGA, the same kind of design as the CPRI example design. Basically, I want to perform a loopback TX to RX in the same core.

- The core is in Slave mode, with Slave Transmit Enable, with singla 3.072 G rate.

- The core is generated with Shared Logic in the core. 

- For clocking, I use recclk into an OBUFDS, then the clock is going into the Si5328. The Si5328 is configured in free run mode then generate my refclk, at 153,6 MHz. The loop bandwidth filter is as high as possible (2,2 Hz).

 

The following observations are made:

- Compared to the example design, iq_tx_enable stays low. So I use the basic_frame_word_first signal to generate my tx-strobe. Why does the iq_tx_enable stays low in hardware? In simulation, that signal is generated by the core and is used to generate the tx_strobe.

- recclk_ok goes high but clk_ok_out stays low. I was unable to bring this up using multiple clock configuation. 

- I tried the Near end PMA Loopback mode and I don't see any activity on rxcharisk, rxdata and rxchariscomma.

- Using a fiber, I performed a TX to RX loopback and I see pretty much random behaviour on rxcharisk, rxdata and rxchariscomma.

- Also, the output pins rxrecclkout, rec_clk and clk_out all have a frequency value of 30.72 MHz. But with a rate of 3.072 G, it shouldn't be that frequency, it should be 153,6 MHz.

 

From my search on the forums, it seems to be clock related but the output of the Si5328 looks pretty clean to me. Should I use RXRECCLKOUT? I tried but failed to instiate the OBUFDS_GTE4, yet.

 

Any help would be much appreciated and if I wasn't clear on any specific point, I would be happy to provide additional info.

 

Regards,

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Registered: ‎06-04-2018

Re: CPRI v8.8 PMA Loopback and Physical Loopback fail on ZCU102 in Vivado 2017.4

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Hi xud,

 

thanks for your reply. Just before just sent your reply, I went back to the example design since I was sure I forgot something. The fact is I had forgot to connect alignment signals such as: txdlysreset_out, txphalign_out and txphinit_out. The Near end PMA loopback worked after that. Also, I receive random signals with an unconnected optical cage on SFP0 which makes my optical cable loopback to fail. I switched to SFP1 cage and my optical cable loopback is now working.

 

So yeah, I should have played more carefully with the example design before going on hardware.

 

Regards,

 

JB

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

Re: CPRI v8.8 PMA Loopback and Physical Loopback fail on ZCU102 in Vivado 2017.4

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jb.larouche@serma.com

 

Have you tested the ZCU102 demo design? You can get it from CPRI lounge : https://www.xilinx.com/member/cpri_eval.html

 

What's the stat_code value in your test? What's the revision of your ZCU102 board?

Regards,

Xu

 

 

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356 Views
Registered: ‎06-04-2018

Re: CPRI v8.8 PMA Loopback and Physical Loopback fail on ZCU102 in Vivado 2017.4

Jump to solution

Hi xud,

 

thanks for your reply. Just before just sent your reply, I went back to the example design since I was sure I forgot something. The fact is I had forgot to connect alignment signals such as: txdlysreset_out, txphalign_out and txphinit_out. The Near end PMA loopback worked after that. Also, I receive random signals with an unconnected optical cage on SFP0 which makes my optical cable loopback to fail. I switched to SFP1 cage and my optical cable loopback is now working.

 

So yeah, I should have played more carefully with the example design before going on hardware.

 

Regards,

 

JB

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