12-17-2013 05:14 PM
I have a 4-Lane 4-Byte Aurora8b10b 8.3 with a Simplex channel that uses framing and side-channel for feedback. The TX side is a XC7K325T-FFG900 an I'm using GTXE2_CHANNEL_X0Y0-X0Y03. On the RX side there is a XC7VX690T-FF1761 and I’m using GTHE2_CHANNEL_X1Y20-X1Y23. I am able to get all 4 lanes and the channel up on Aurora. I also don’t receive any errors (CRC_FAIL, hard, soft, frame) as the problem is happening. I observe this problem even when using the sample design that is generated with aurora.
Here is my problem, I send the following data over the TXD bus…
11111111_11111111_11111111_11111111 (1 cycle on the 128-bit TXD bus)
And this is what I have on RXD bus:
11112222_22222222_11111111_11111111 (1 cycle on the 128-bit RXD bus)
4444xxxx _ xxxx xxxx _44444444_44444444
I have noticed that at the end of a frame (tlast = 1) rx_tkeep doesn’t match what I feed to tx_tkeep(which is always 0xFFFF).
Lastly I have noticed that when using aurora 8.3 and GT_Wizard 2.6 the produced *_gt.vhd from the wizard has to be slightly modified before it can work with Aurora. The Aurora IP documentation seems to imply is should be a simple drag and drop. I would just like to make sure there is an versioning problem on my end.
Any help is appreciated.
12-18-2013 11:08 AM
12-18-2013 03:41 PM
Thanks for your answer. I attached 4 pictures - all related to the rx side.
1. shows the lines you asked for, things seems to be ok for me
2. a closer look to the data_valid, last etc
3. a more closer look to the data, and you can see the data skew
4. shows the frame_err and the behavior after that.
I don't know if the frame_err is related to this data skew, I would like to think that it is. I have checked and I don't get any soft errors. I thougth the frame_err s are caused by the soft errors most of the time - I guess this is not the case here.
12-18-2013 03:41 PM
Here I attached the 4th picture.
Can you please let me know what you think?
Any help is appreciated!
03-30-2015 02:13 AM
I want to know whether your problem have been solved. I have encountered the same issue recently when I have two fpgas connected with four lanes' aurora link.
Waiting for your reply!
04-01-2015 08:04 AM