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Adventurer
Adventurer
2,420 Views
Registered: ‎04-22-2016

Does Serial RapidIO Gen2 Endpoint logiCORE IP support “RapidIO Gen 2.1 specification” ?

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Dear All,

Now,  I'm trying to implement with Serial RapidIO Gen2 IP. But this is the first time what I run with this.

So I'd like to run with example  testbench on Serial RapidIO Gen2 IP. 

but I can't find it. Would you please help me how to find this example with testbench code in Vivado?

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Xilinx Employee
Xilinx Employee
4,409 Views
Registered: ‎02-06-2013

Re: Does Serial RapidIO Gen2 Endpoint logiCORE IP support “RapidIO Gen 2.1 specification” ?

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Hi

 

Xilinx SRIO GEN2 core is designed as per rev 2.2 spec but the core is back ward compatible with rev 2.1 spec.

 

In vivado after generating the core, select the xci and right click to see open example design option which will create a new project with the example design and test bench files.

Regards,

Satish

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3 Replies
Xilinx Employee
Xilinx Employee
4,410 Views
Registered: ‎02-06-2013

Re: Does Serial RapidIO Gen2 Endpoint logiCORE IP support “RapidIO Gen 2.1 specification” ?

Jump to solution

Hi

 

Xilinx SRIO GEN2 core is designed as per rev 2.2 spec but the core is back ward compatible with rev 2.1 spec.

 

In vivado after generating the core, select the xci and right click to see open example design option which will create a new project with the example design and test bench files.

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
Adventurer
Adventurer
2,405 Views
Registered: ‎04-22-2016

Re: Does Serial RapidIO Gen2 Endpoint logiCORE IP support “RapidIO Gen 2.1 specification” ?

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hello satish ?
can I simulate that example codes in ncverilog? not in the vivado?

and one more thing, can I got the verilog teshbench not VHDL?

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Xilinx Employee
Xilinx Employee
2,395 Views
Registered: ‎02-06-2013

Re: Does Serial RapidIO Gen2 Endpoint logiCORE IP support “RapidIO Gen 2.1 specification” ?

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Hi

 

Yes you can simulate the core ncsim.

 

Example design and test bench are generated in Verilog.

Regards,

Satish

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