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Newbie ryan252019
Newbie
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Registered: ‎02-04-2019

Ethernet implementation using LVDS

Hi. I am trying to research on an option of using Ethernet 100 Base-TX over LVDS for a multidrop backplane module.

I would like to know the following:

1. Is there any reference design that talks about such an implementation?

2 Do you have an IP Core that has an MII Interface to connect with my Host CPU on one side, an uses the built in Ser/Des that uses built-in LVDS trancievers to generate the LVDS level signals. (Basically the IP core will need to emulate an 100Base TX Ethernet PHY and instead of generate the MLT3 output, we will use the LVDS)? Is this something we can model with available cores from Xilinx?

 

Thanks

Ryan

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