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Visitor raymondxuym
Visitor
1,619 Views
Registered: ‎09-11-2017

Failed to set IOSTANDARD of a CLK PIN of Zynq Ultrascale +

Hi there:

 

I have a Zynq Ultrascale+ (xzcu102) and i was trying to make the GTH transceiver works.

The PCIe is connected to a FMC daughter card and takes the ref clk from the card.

However, the clk from the daughter card is LVDS, when I tried to set_property LVDS for the PCIe ref clk at FPGA, it returns:

 

[Vivado 12-1815] Setting property 'IOSTANDARD' is not allowed for GT terminals.

 

Beside, I cannot find the SelectIO Resources User Guide for Ultrascale+. Only Ultrascale, Spartan, Virtex6, 7 series avaliable.

When i type command get_io_standard in vivado, it seems no LVDS supported in this board. (Only LVDS_25, Sub_LVDS..)

 

 

Does anyone know how can i set the IOSTANDARD?

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2 Replies
Xilinx Employee
Xilinx Employee
1,584 Views
Registered: ‎05-01-2013

Re: Failed to set IOSTANDARD of a CLK PIN of Zynq Ultrascale +

You don't need to set any IOSTANDARD for GT reference clock. It's fixed CML

It can be connected to LVDS by AC coupling.

GT User Guide has more details.

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Xilinx Employee
Xilinx Employee
1,532 Views
Registered: ‎02-06-2013

Re: Failed to set IOSTANDARD of a CLK PIN of Zynq Ultrascale +

Hi

 

UG571 is the Select IO user guide for Ultrascale Architecture(it is applicable to both ultrascale and ulstrascale+ devices)

Regards,

Satish

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