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Observer yeemanb
Observer
8,725 Views
Registered: ‎11-20-2009

Getting GMII tri speed example design for v5_emac_v1_6 to work on the ML505 board

Hi,

 

I've been trying to get the example design for the v5_emac_v1_6 wrapper to work on the ML505 board.

 

I placed the following with the help of the schematic at

http://www.xilinx.com/support/documentation/boards_and_kits/ml50x_schematics.pdf

 

 

INST "gmii_txd_0<0>"     LOC = "AF11";
INST "gmii_txd_0<1>"     LOC = "AE11";
INST "gmii_txd_0<2>"     LOC = "AH9";
INST "gmii_txd_0<3>"     LOC = "AH10";
INST "gmii_txd_0<4>"     LOC = "AG8";
INST "gmii_txd_0<5>"     LOC = "AH8";
INST "gmii_txd_0<6>"     LOC = "AG10";
INST "gmii_txd_0<7>"     LOC = "AG11";
INST "gmii_tx_en_0"      LOC = "AJ10";
INST "gmii_tx_er_0"      LOC = "AJ9";
INST "gmii_tx_clk_0"     LOC = "K17";

INST "gmii_rxd_0<0>"     LOC = "A33";
INST "gmii_rxd_0<1>"     LOC = "B33";
INST "gmii_rxd_0<2>"     LOC = "C33";
INST "gmii_rxd_0<3>"     LOC = "C32";
INST "gmii_rxd_0<4>"     LOC = "D32";
INST "gmii_rxd_0<5>"     LOC = "C34";
INST "gmii_rxd_0<6>"     LOC = "D34";
INST "gmii_rxd_0<7>"     LOC = "F33";
INST "gmii_rx_dv_0"      LOC = "E32";
INST "gmii_rx_er_0"      LOC = "E33";
INST "gmii_rx_clk_0"     LOC = "H17";#"H14";

 

INST "RESET"             LOC = "U8";  #push button north

 

# Place BUFG to prevent prevent placement skewing IODELAY value
INST "bufg_phy_rx_0"     LOC = "BUFGCTRL_X0Y31";

# 125MHz reference clock
INST "GTX_CLK_0"         IOSTANDARD = LVTTL;
INST "GTX_CLK_0"         LOC = "J16";

# 200MHz IDELAY controller clock
INST "REFCLK"            IOSTANDARD = LVTTL;
INST "REFCLK"            LOC = "L19";

 

 

When I run the design, all the PHY related LEDs go off.

 

Can someone spot what I wired wrong?

 

Other Details:

1) Yes, my J22, J23, J24, J56 jumpers are correct according to the User Guide

2) I was not sure how to place MII_TX_CLK_0.

3) When I try to place

INST "gmii_col_0"        LOC = "B32";
INST "gmii_crs_0"        LOC = "E34";
Map gave me an error on conflicting standards.

 

 

Thanks!

YeeMan

 

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8 Replies
Observer yeemanb
Observer
8,716 Views
Registered: ‎11-20-2009

Re: Getting GMII tri speed example design for v5_emac_v1_6 to work on the ML505 board

Hi,

 

I got the PHY DUP and 1000 lights to go on after I added

 

INST "gmii_col_0"        IOSTANDARD = LVTTL;
INST "gmii_crs_0"        IOSTANDARD = LVTTL;

INST "gmii_col_0"        LOC = "B32";
INST "gmii_crs_0"        LOC = "E34";

 

# ML505 gpio north push button
NET "RESET" LOC = "U8";
NET "RESET" PULLUP;

 

# ML505 PHY Reset
NET "PHY_RESET_0"        IOSTANDARD = LVTTL;
NET "PHY_RESET_0"        LOC = "J14";

 

The TX light still does not work.

I guess I'll use ChipScope next to see where it is holding up.

 

If anyone has experience on getting GMII tri speed to work on the ML505, any pointers would be nice.

 

 

Thanks!

YeeMan

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Observer yeemanb
Observer
8,706 Views
Registered: ‎11-20-2009

Re: Getting GMII tri speed example design for v5_emac_v1_6 to work on the ML505 board

Hi,

 

In Chipscope, I can see data coming from the PHY to the EMAC

 

    GMII_RXD_0,
    GMII_RX_DV_0,
    GMII_RX_ER_0,
    GMII_RX_CLK_0 ,

But there is no data coming from the Local link FIFO to the address swap module.

 

I will keep tracing down.  Anyone else experienced this and know the fix?

 

Thanks!

YeeMan

 

 

 

 

 

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Observer yeemanb
Observer
8,701 Views
Registered: ‎11-20-2009

Re: Getting GMII tri speed example design for v5_emac_v1_6 to work on the ML505 board

Hi Everyone,

 

Ok, so I changed my connection to GTX_CLK_0.

I am now getting data to and from the address swap module.

I am still not seeing the TX LED on or anything from wireshark.

 

 

It would be better if the generated example designs worked right out of the wizard.

 Or somewhere on the xilinx site where we can download working example designs for specific evaluation boards.

 

 

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Visitor pengyanj
Visitor
8,639 Views
Registered: ‎02-16-2010

Re: Getting GMII tri speed example design for v5_emac_v1_6 to work on the ML505 board

did you try to turn on the auto negotiation in your ucf or vhd top file?

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Visitor ahartnet
Visitor
8,288 Views
Registered: ‎05-11-2010

Re: Getting GMII tri speed example design for v5_emac_v1_6 to work on the ML505 board

Yeemanb,

 

I am having a similar issue. I'm using wireshark and I can see that the data is being sent to the board, but the board is not doing the address swap and sending it back. What do you mean by you changed your connection to GTX_CLK_0? What connection did you change?

 

Thanks

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Visitor vkarasen
Visitor
7,707 Views
Registered: ‎07-27-2010

Re: Getting GMII tri speed example design for v5_emac_v1_6 to work on the ML505 board

hello all,

 

I am having the same problems as the others here. I changed the design insofar as I generated the refclk and the gtx_clk from a pll because the ml505 doesnt provide a single-ended 200MHz clock signal. I do see the rx led blinking when I send a packet to the FPGA, but I don't see anything happening in Wireshark and some rather primitive tests I made also don't give any clue what might be wrong. I suppose that the biggest uncertainity is in the ucf files as the rtl simulation in modelsim was fine. It would be nice if someone had a working ucf file for the ml505 board for me

 

regards vkarasen

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Xilinx Employee
Xilinx Employee
7,696 Views
Registered: ‎04-16-2008

Re: Getting GMII tri speed example design for v5_emac_v1_6 to work on the ML505 board

XAPP957 provides a working demo of GMII on the ML505 board.

http://www.xilinx.com/support/documentation/application_notes/xapp957.pdf

 

If you would like to just use the example design and target the ML505 I'd recommend:

1) using the ucf from XAPP957

2) using DCM to generate a 125Mhz clock (you could copy over the one from the xapp)

3) the phy reset that is connected to an FPGA output must be driven with an active low reset (the inverse of the reset to the TEMAC)

 

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Visitor tomkan
Visitor
6,257 Views
Registered: ‎10-24-2012

Re: Getting GMII tri speed example design for v5_emac_v1_6 to work on the ML505 board

Hi all:

I've been trying to get the example design for the v5_emac_v1_8 wrapper to work on the ML507 board.

 

here is my ucf:

NET "GMII_TXD_0[0]" IOSTANDARD = LVDCI_33;
NET "GMII_TXD_0[0]" LOC = AF11;
NET "GMII_TXD_0[1]" IOSTANDARD = LVDCI_33;
NET "GMII_TXD_0[1]" LOC = AE11;
NET "GMII_TXD_0[2]" IOSTANDARD = LVDCI_33;
NET "GMII_TXD_0[2]" LOC = AH9;
NET "GMII_TXD_0[3]" IOSTANDARD = LVDCI_33;
NET "GMII_TXD_0[3]" LOC = AH10;
NET "GMII_TXD_0[4]" IOSTANDARD = LVDCI_33;
NET "GMII_TXD_0[4]" LOC = AG8;
NET "GMII_TXD_0[5]" IOSTANDARD = LVDCI_33;
NET "GMII_TXD_0[5]" LOC = AH8;
NET "GMII_TXD_0[6]" IOSTANDARD = LVDCI_33;
NET "GMII_TXD_0[6]" LOC = AG10;
NET "GMII_TXD_0[7]" IOSTANDARD = LVDCI_33;
NET "GMII_TXD_0[7]" LOC = AG11;
NET "GMII_TX_EN_0" IOSTANDARD = LVDCI_33;
NET "GMII_TX_EN_0" LOC = AJ10;
NET "GMII_TX_ER_0" IOSTANDARD = LVDCI_33;
NET "GMII_TX_ER_0" LOC = AJ9;
NET "GMII_TX_CLK_0" IOSTANDARD = LVCMOS25;
NET "GMII_TX_CLK_0" LOC = K17;

NET "GMII_RXD_0[0]" IOSTANDARD = LVCMOS25;
NET "GMII_RXD_0[0]" LOC = A33;
NET "GMII_RXD_0[1]" IOSTANDARD = LVCMOS25;
NET "GMII_RXD_0[1]" LOC = B33;
NET "GMII_RXD_0[2]" IOSTANDARD = LVCMOS25;
NET "GMII_RXD_0[2]" LOC = C33;
NET "GMII_RXD_0[3]" IOSTANDARD = LVCMOS25;
NET "GMII_RXD_0[3]" LOC = C32;
NET "GMII_RXD_0[4]" IOSTANDARD = LVCMOS25;
NET "GMII_RXD_0[4]" LOC = D32;
NET "GMII_RXD_0[5]" IOSTANDARD = LVCMOS25;
NET "GMII_RXD_0[5]" LOC = C34;
NET "GMII_RXD_0[6]" IOSTANDARD = LVCMOS25;
NET "GMII_RXD_0[6]" LOC = D34;
NET "GMII_RXD_0[7]" IOSTANDARD = LVCMOS25;
NET "GMII_RXD_0[7]" LOC = F33;
NET "GMII_RX_DV_0" IOSTANDARD = LVCMOS25;
NET "GMII_RX_DV_0" LOC = E32;
NET "GMII_RX_ER_0" IOSTANDARD = LVCMOS25;
NET "GMII_RX_ER_0" LOC = E33;
NET "GMII_RX_CLK_0" IOSTANDARD = LVCMOS25;
NET "GMII_RX_CLK_0" LOC = H17;

 

NET "CLKIN1_N_IN" IOSTANDARD = LVDS_25;
NET "CLKIN1_N_IN" LOC = K19;
NET "CLKIN1_P_IN" IOSTANDARD = LVDS_25;
NET "CLKIN1_P_IN" LOC = L19;


NET "GMII_COL_0" LOC = B32;
NET "GMII_CRS_0" IOSTANDARD = LVCMOS25;
NET "GMII_CRS_0" LOC = E34;
NET "PHY_RESET" IOSTANDARD = LVCMOS25;
NET "PHY_RESET" LOC = J14;
NET "RESET" LOC = U8;


NET "GMII_COL_0" IOSTANDARD = LVCMOS25;
NET "RESET" IOSTANDARD = LVCMOS33;


NET "CLKIN1_IN" LOC = AH15;

NET "CLKIN1_IN" IOSTANDARD = LVCMOS33;

 

I use two PLL(CLKIN1_IN,CLKIN1_N_IN,CLKIN1_P_IN),generate 200Mhz to REFCLK and 125Mhz to MII_TX_CLK_0,GTX_CLK_0.

 

When I download the bit file to FPGA, all the PHY related LEDs go off.

 

Here's what I do:

1: I'm using GMII interface; so set the jumper J22 & J23 to 1-2

2: I set the DIP SW6 at the back of the board to 00111010 to get 125MHz clock for Ethernet PHY

 

Help ME!!

Thank you very much.

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