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Visitor myfpgadevel
Visitor
3,714 Views
Registered: ‎09-01-2010

Host Controller in 10G EMAC IP Core

 I try to comunicate with host controller at 10G EMAC IP Core. Created FSM that implement signal sequence such as in UG148 User Guide to IP Core. But i can't receive any answer from host controller. My FSM implement following steps:

1. Write 6'b111000 to host controller register with address 0x340. (Try to enable MDIO, host_clk == 125 MHz)

2. Read data from host controller register with address 0x340.

What is wrong? May be IP Core should be prepared with additional signal sequence?

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2 Replies
Explorer
Explorer
3,627 Views
Registered: ‎10-01-2008

Re: Host Controller in 10G EMAC IP Core

Hi,

 

I would suggest you run a simulation using the default testbench (it is generated with the 10GEMAC core) and compare the host interface waveform with yours. The code is written like the following in the TB.

 

 

  p_management : process
  begin
    wait until reset = '0';
    assert false
      report "Waiting for DCM's to obtain lock..."
      severity note;
    wait for 600 ns;                      -- wait for DCM's to obtain lock
    ---------------------------------------------------------------------------
    -- set up MDC frequency
    assert false
      report "Setting MDC Frequency...."
      severity note; wait until host_clk'event and host_clk = '0';
    host_addr(9)          <= '1';
    host_miim_sel         <= '0';
    host_opcode           <= "11";
    host_addr(8 downto 0) <= CONFIG_MANAGEMENT;
    wait until host_clk'event and host_clk = '0';
    -- set CLOCK_DIVIDE value to 11 dec. for 52.08 MHz HOST_CLK and enable MIIM
    host_wr_data          <= host_rd_data(31 downto 6) & "101011";
    host_opcode           <= "01";
    wait until host_clk'event and host_clk = '0';
    -- turn off flow control in both directions
    assert false
      report "Disabling flow control..."
      severity note;
    -- read the current config value from the register.
    host_addr(8 downto 0) <= CONFIG_FLOW_CTRL;
    host_opcode           <= "11";
    -- now turn off the relevant bits and write back into the register
    wait until host_clk'event and host_clk = '0';
    host_wr_data          <= "000" & host_rd_data(28 downto 0);
    host_opcode           <= "01";
    wait until host_clk'event and host_clk = '0';
    host_opcode           <= "11";        -- back to read operation for safety
    
    -- semaphore to the other processors to start work
    configuration_finished <= true;
    management_finished <= true;
  end process p_management;

 

 

The provided TB should help us understand how to control the host interface. Hope this will help you.

 

-Yan Shun Li

 

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Visitor myfpgadevel
Visitor
3,475 Views
Registered: ‎09-01-2010

Re: Host Controller in 10G EMAC IP Core

Thank you

 

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